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AD7226

LC2MOS Quad 8-Bit D/A Converter

Analog Devices 

AD7226

INTERFACE LOGIC INFORMATION

Address lines A0 and A1 select which DAC will accept data

from the input port. Table I shows the selection table for the

four DACs with Figure 4 showing the input control logic. When

the WR signal is LOW, the input latches of the selected DAC

are transparent and its output responds to activity on the data

bus. The data is latched into the addressed DAC latch on the

rising edge of WR. While WR is high the analog outputs remain

at the value corresponding to the data held in their respective latches.

Table I. AD7226 Truth Table

AD7226 Control Inputs AD7226

WR

A1

A0 Operation

H

X

X No Operation Device Not Selected

L

L

L DAC A Transparent

L

L DAC A Latched

L

L

H DAC B Transparent

L

H DAC B Latched

L

H

L DAC C Transparent

H

L DAC C Latched

L

H

H DAC D Transparent

H

H DAC D Latched

L = Low State, H = High State, X = Don’t Care

A0

TO LATCH A

A1

TO LATCH B

TO LATCH C

TO LATCH D

WR

Figure 4. Input Control Logic

DATA

ADDRESS

tAS

VINH

VINL

tDS

VINH

VINL

tDH

tAH

VDD

0

VDD

0

WR

tWR

VDD

0

NOTES

1. ALL INPUT SIGNAL RISE AND FALL TIMES

MEASURED FROM 10% TO 90% OF VDD.

tr = tf = 20ns OVER VDD RANGE.

2. TIMING MEASUREMENT REFERENCE LEVEL IS

VINH + VINL

2

3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS

LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE

SPURIOUS OUTPUTS.

Figure 5. Write Cycle Timing Diagram

–6–

REV. D

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