MX7576D Ver la hoja de datos (PDF) - Maxim Integrated

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MX7576D

CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs

Maxim Integrated 

CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs

CS

RD

t1

t5

BUSY

t2

tCONV

DATA

t3

HIGH-

IMPEDANCE

BUS

t6

OLD DATA

t7

NEW

DATA

HIGH-

IMPEDANCE

BUS

Figure 3. Slow-Memory Interface Timing Diagram

CS

t1

RD

t4

t2

BUSY

t3

HIGH-

DATA IMPEDANCE

BUS

OLD

DATA

t5

t8

t7

t3

HIGH-IMPEDANCE BUS

Figure 5. ROM Interface Timing Diagram

t7

NEW

DATA

HIGH-

IMPEDANCE

BUS

A8–A15

8085A-2

S0

ALE

ADDRESS BUS

+5V

TP/MODE

ADDRESS

DECODE

CS MX7575*

RD MX7576

ADDRESS

LATCH

BUSY

D0–D7

AD0–AD7

READY

DATA BUS

* SOME CIRCUITRY OMITTED FOR CLARITY

S0 IS LOW FOR READ CYCLES

Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface

A0–A15

6502-6809

R/W

Φ 2 OR E

ADDRESS BUS

+5V

TP/MODE

EN

ADDRESS

DECODE

CS MX7575*

MX7576

RD

D0–D7

D0–D7

DATA BUS

* SOME CIRCUITRY OMITTED FOR CLARITY

Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface

including the 8085A-2, test the status of the READY

input immediately after the start of an instruction cycle.

Therefore, if the MX7575/MX7576 are to be effective in

placing the µP in a wait state, their BUSY output should

go low very early in the cycle. When using the 8085A-2,

the earliest possible indication of an upcoming read

operation is provided by the S0 status signal. Thus, S0,

which is low for a read cycle, should be connected to

the RD input of the MX7575/MX7576. Figure 4 shows

the connection diagram for the 8085A-2 to the

MX7575/MX7576 in slow-memory interface mode.

ROM Interface Mode

Figure 5 shows the timing diagram for ROM interface

mode. In this mode, the µP does not need to be placed

in a wait state. A conversion is started with a read

instruction (RD and CS go low), and old data is

accessed. The BUSY signal then goes low to indicate

the start of a conversion. As before, the MX7575

track/hold acquires the signal on the third falling clock

edge after RD goes low, while the MX7576 samples it

eight times during a conversion. At the end of a conver-

sion (BUSY going high), another read instruction always

accesses the new data and normally starts a second

conversion. However, if RD and CS go low within one

external clock period of BUSY going high, then the sec-

ond conversion is not started. Furthermore, for correct

operation in this mode, RD and CS should not go low

before BUSY returns high.

Figures 6 and 7 show the connection diagrams for

interfacing the MX7575/MX7576 in the ROM interface

mode. Figure 6 shows the connection diagram for the

6502/6809 µPs, and Figure 7 shows the connections for

the Z-80.

Due to their fast interface timing, the MX7575/MX7576

will interface to the TMS32010 running at up to 18MHz.

Figure 8 shows the connection diagram for the

TMS32010. In this example, the MX7575/MX7576 are

mapped as a port address. A conversion is initiated by

using an IN A and a PA instruction, and the conversion

result is placed in the TMS32010 accumulator.

Asynchronous Conversion Mode (MX7576)

Tying the MODE pin low places the MX7576 into a con-

tinuous conversion mode. The RD and CS inputs are

only used for reading data from the converter. Figure 9

shows the timing diagram for this mode of operation,

and Figure 10 shows the connection diagram for the

8085A. In this mode, the MX7576 looks like a ROM to

6 _______________________________________________________________________________________

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