MX7576 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MX7576 Datasheet PDF : 12 Pages
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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V; VREF = 1.23V; AGND = DGND = 0V; fCLK = 4MHz external for MX7575; fCLK = 2MHz external for MX7576;
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLOCK
Input Low Voltage
VINL
Input High Voltage
VINH
2.4
Input Low Current
IINL
VIN = 0V
MX757_J/A/K/B
MX757_S/T
Input High Current
IINH
LOGIC OUTPUTS (D0–D7, BUSY)
VIN = VDD
MX757_J/A/K/B
MX757_S/T
Output Low Voltage
VOL
ISINK = 1.6mA
Output High Voltage
VOH ISOURCE = 40µA
4.0
Floating State Leakage Current
VOUT = 0V to VDD, D0–D7
TA = +25°C
TA = TMIN to TMAX
0.8
V
V
700
µA
800
700
µA
800
0.4
V
V
±1
µA
±10
Floating State Output
Capacitance (Note 2)
D0–D7
10
pF
CONVERSION TIME (Note 3)
Conversion Time with
External Clock
Conversion Time with
Internal Clock
POWER REQUIREMENTS (Note 4)
Supply Voltage
VDD
Supply Current
IDD
Power Dissipation
Power-Supply Rejection
MX7575: fCLK = 4MHz
MX7576: fCLK = 2MHz
Using recommended
clock components:
RCLK = 100kΩ,
CCLK = 100pF;
TA = +25°C
MX7575
MX7576
±5% for specified performance
MX757_J/A/K/B
MX757_S/T
4.75V < VDD < 5.25V
5
µs
10
5
15
µs
10
30
5
V
3
6
mA
7
15
mW
±1/4 LSB
Note 1: Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2: Sample tested at +25°C to ensure compliance.
Note 3: Accuracy may degrade at conversion times other than those specified.
Note 4: Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575 CS = RD = BUSY = high;
For MX7576 CS = RD = BUSY = MODE = high.
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