MX7575 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MX7575 Datasheet PDF : 12 Pages
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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
+5V
R6
3.3k
0.1µF 47µF + ICL8069
1.2V
REFERENCE
+5V
47µF
+5V
TLC271
R5
5k
R4
8.2k
+5V
0.1µF
18
17
VDD
REF CLK
5
MX7575
RCLK
CL
100pF
2%
R1
1k
16 AIN
D7–D0
AGND
R8220Ω15
DGND
9
DATA OUT
R7
R3
10k
500Ω
INPUT VOLTAGE
Figure 18a. MX7575 Bipolar Configuration
__________Applications Information
Noise
To minimize noise coupling, keep both the input signal
lead to AIN and the signal return lead from AGND as
short as possible. If this is not possible, a shielded
cable or a twisted-pair transmission line is recommend-
ed. Additionally, potential differences between the ADC
ground and the signal-source ground should be mini-
mized, since these voltage differences appear as
errors superimposed on the input signal. To minimize
system noise pickup, keep the driving source resis-
tance below 2kΩ.
Proper Layout
For PC board layouts, take care to keep digital lines
well separated from any analog lines. Establish a sin-
gle-point, analog ground (separate from the digital sys-
tem ground) near the MX7575/MX7576. This analog
ground point should be connected to the digital system
ground through a single-track connection only. Any
supply or reference bypass capacitors, analog input fil-
ter capacitors, or input signal shielding should be
returned to the analog ground point.
OUTPUT
CODE
111...111
111...110
100...010
100...001 -FS
100...000 2
011...111
011...110
-1/2LSB
1/2LSB
AIN
FS -1LSB
2
000...001
000...000
FS = 2VREF
1LSB =
2FS
256
Figure 18b. Nominal Transfer Characteristic for Bipolar
Operation
__Functional Diagrams (continued)
AIN 16
AGND 15
MX7576
REF 17
CLK 5
CLOCK
OSCILLATOR
CS
RD
1
2
MODE 3
CONTROL
LOGIC
4
BUSY
VDD
18
COMP
DAC
SAR
LATCH AND
THREE-STATE
OUTPUT DRIVERS
9
DGND
..6
D7
D0
14
______________________________________________________________________________________ 11
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