ADG714BRUZ-REEL7(RevE) Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

ADG714BRUZ-REEL7
(Rev.:RevE)

CMOS, Low Voltage Serially Controlled, Octal SPST Switches

Analog Devices 

Data Sheet

ADG714/ADG715

GND 1

S1 2

D1 3

S2 4

D2 5

S3 6

ADG714

TOP VIEW

(Not to Scale)

18 VSS

17 S8

16 D8

15 S7

14 D7

13 S6

Table 9. ADG714 Pin Function Descriptions

Pin No.

Mnemonic

1

GND

2, 4, 6, 8, 11, 13, 15, 17 Sx

3, 5, 7, 9, 10, 12, 14, 16 Dx

18

VSS

19

DOUT

20

RESET

21

SYNC

22

SCLK

23

VDD

24

DIN

EP

EP

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, VSS.

Figure 6. ADG714 LFCSP Pin Configuration

Description

Ground (0 V) Reference.

Source. These pins may be an input or an output.

Drain. These pins may be an input or an output.

Most Negative Power Supply Potential. In single-supply applications, VSS is

connected to ground.

Serial Data Output. This pin is used for daisy-chaining a number of these devices

together or for reading back data in the shift register for diagnostic purposes. The

serial data is transferred on the rising edge of SCLK and is valid on the falling edge

of the clock. Pull this open-drain output to the supply with an external resistor.

RESET. Under normal operation, drive the RESET pin with a 2.7 V to 5 V supply. Pull

the pin low (<0.8 V) for a short period (15 ns is sufficient) to complete a hardware

reset. All switches are opened and the appropriate registers are cleared to 0.

When using the RESET pin to complete a hardware reset, all other SPI pins (SYNC,

SCLK, and DIN) must be driven low.

Active Low Control Input. This pin is the frame synchronization signal for the input

data. When SYNC goes low, this pin powers on the SCLK and DIN buffers and

enables the input shift register. Data is transferred in on the falling edges of the

following clock cycle. Taking SYNC high updates the switch condition.

Serial Clock Input. Data is clocked into the input shift register on the falling edge

of the serial clock input. Data is transferred at rates of up to 50 MHz.

Most Positive Power Supply Potential.

Serial Data Input. This device has an 8-bit shift register. Data is clocked into the

register on the falling edge of the serial clock input.

Exposed Pad. Exposed pad tied to the substrate, VSS.

Rev. E | Page 11 of 21

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