ADG714(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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ADG714 Datasheet PDF : 16 Pages
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ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1 (VDD = 2.7 V to 5.5 V. All specifications –40؇C to +85؇C unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCL
400
t1
2.5
t2
0.6
t3
1.3
t4
0.6
t5
100
t62
0.9
0
t7
0.6
t8
0.6
t9
1.3
t10
300
20 + 0.1Cb3
t11
250
t11
300
20 + 0.1Cb3
Cb
400
tSP4
50
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns max
ns min
pF max
ns max
SCL Clock Frequency
SCL Cycle Time
tHIGH, SCL High Time
tLOW, SCL Low Time
tHD, STA, Start/Repeated Start Condition Hold Time
tSU, DAT, Data Setup Time
tHD, DAT, Data Hold Time
tSU, STA, Setup Time for Repeated Start
tSU, STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and
a Start Condition
tR, Rise Time of both SCL and SDA when Receiving
tF, Fall Time of SDA When Receiving
tF, Fall Time of SDA when Transmitting
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
NOTES
1See Figure 2.
2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
4Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t2
t6
t5
t7
t1
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
STOP
CONDITION
–6–
REV. 0
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