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Fabricante

AD7713
(Rev.:RevC)

LC2MOS Loop-Powered Signal Conditioning ADC

Analog Devices 

Pin Mnemonic

1 SCLK

2 MCLK IN

3 MCLK OUT

4 A0

5 SYNC

6 MODE

7 AIN1(+)

8 AIN1(–)

9 AIN2(+)

10 AIN2(–)

11 STANDBY

12 AVDD

13 RTD1

14 REF IN(–)

15 REF IN(+)

16 RTD2

17 AIN3

18 AGND

19 TFS

20 RFS

AD7713

PIN FUNCTION DESCRIPTION

Function

Serial Clock. Logic input/output depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes

active when RFS or TFS goes low and it goes high impedance when either RFS or TFS returns high or when

the device has completed transmission of an output word. When MODE is low, the device is in its external

clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all

2

data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the

information being transmitted to the AD7713 in smaller batches of data.

Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a

CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 2 MHz.

When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

Address Input. With this input low, reading and writing to the device is to the control register. With thisinput

high, access is to either the data register or the calibration registers.

Logic Input which allows for synchronization of the digital filters when using a number of AD7713s. It resets

the nodes of the digital filter.

Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its

external clocking mode.

Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source which can be used to check that an external transducer has burnt out

or gone open circuit. This output current source can be turned on/off via the control register.

Analog Input Channel 1. Negative input of the programmable gain differential analog input.

Analog Input Channel 2. Positive input of the programmable gain differential analog input.

Analog Input Channel 2. Negative input of the programmable gain differential analog input.

Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power

consumption to less than 50 µW.

Analog Positive Supply Voltage, +5 V to +10 V.

Constant Current Output. A nominal 200 µA constant current is provided at this pin and this can be used

as the excitation current for RTDs. This, current can be turned on or off via the control register.

Reference Input. The REF IN(–) can lie anywhere between AVDD and AGND provided REF IN(+) is

greater than REF IN(–).

Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).

REF IN(+) can lie anywhere between AVDD and AGND.

Constant Current Output. A nominal 200 µA constant current is provided at this pin and this can be used

as the excitation current for RTDs. This, current can be turned on or off via the control register. This

second current can be used to eliminate lead resistanced errors in three-wire RTD configurations.

Analog Input Channel 3. High level analog input which accepts an analog input voltage range of

4 × VREF/GAIN. At the nominal VREF of +2.5 V and a gain of 1, the AIN3 input voltage range is

0 to ± 10 V.

Ground Reference Point for Analog Circuitry.

Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial

data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active

after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data word

is written to the part.

Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external

clocking mode, the SDATA line becomes active after RFS goes low.

REV. C

–7–

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