AD7712(RevE) Ver la hoja de datos (PDF) - Analog Devices
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AD7712 Datasheet PDF : 28 Pages
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AD7712–SPECIFICATIONS (AVDD = +5␣ V ؎ 5%; DVDD = +5␣ V ؎ 5%; VSS = 0␣ V or –5 V ؎ 5%; REF IN(+) = +2.5␣ V;
REF IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise stated. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A, S Versions1
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity @ +25°C
TMIN to TMAX
Positive Full-Scale Error2, 3
Full-Scale Drift5
Unipolar Offset Error2
Unipolar Offset Drift5
Bipolar Zero Error2
Bipolar Zero Drift5
Gain Drift
Bipolar Negative Full-Scale Error2 @ +25°C
TMIN to TMAX
Bipolar Negative Full-Scale Drift5
24
22
18
15
12
See Tables I & II
± 0.0015
± 0.003
See Note 4
1
0.3
See Note 4
0.5
0.25
See Note 4
0.5
0.25
2
± 0.003
± 0.006
1
0.3
Bits min
Bits min
Bits min
Bits min
Bits min
% FSR max
% FSR max
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
ppm/°C typ
% FSR max
% FSR max
µV/°C typ
µV/°C typ
Guaranteed by Design. For Filter Notches ≤ 60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches ≤ 60 Hz
Typically ± 0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Excluding Reference
Typically ± 0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Normal-Mode 50 Hz Rejection6
Normal-Mode 60 Hz Rejection6
AIN1/REF IN
DC Input Leakage Current @ +25°C6
TMIN to TMAX
Sampling Capacitance6
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection6
Common-Mode 60 Hz Rejection6
Common-Mode Voltage Range7
Analog Inputs8
Input Sampling Rate, fS
AIN1 Input Voltage Range9
AIN2 Input Voltage Range9
AIN2 DC Input Impedance
AIN2 Gain Error11
AIN2 Gain Drift
AIN2 Offset Error11
AIN2 Offset Drift
Reference Inputs
REF IN(+) – REF IN(–) Voltage12
Input Sampling Rate, fS
100
100
10
1
20
100
150
150
VSS to AVDD
See Table III
0 to +VREF10
± VREF
0 to + 4 × VREF10
± 4 × VREF
30
± 0.05
1
10
20
+2.5 to +5
fCLK IN/256
dB min
dB min
pA max
nA max
pF max
dB min
dB min
dB min
V min to V max
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × fNOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 × fNOTCH
At DC
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 × fNOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 × fNOTCH
V max
V max
V max
V max
kΩ
% typ
ppm/°C typ
mV max
µV/°C typ
V min to V max
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
Additional Error Contributed by Resistor Attenuator
Additional Drift Contributed by Resistor Attenuator
Additional Error Contributed by Resistor Attenuator
For Specified Performance. Part Is Functional with
Lower VREF Voltages
NOTES
1Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.
2Applies after calibration at the temperature of interest.
3Positive full-scale error applies to both unipolar and bipolar input ranges.
4These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6These numbers are guaranteed by design and/or characterization.
7This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV DD + 30 mV and VSS – 30 mV.
8The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).
9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV DD + 30 mV or more negative than VSS – 30 mV.
10VREF = REF IN(+) – REF IN(–).
11This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the STATIC PERFORMANCE section.
12The reference input voltage range may be restricted by the input voltage range requirement on the V BIAS input.
–2–
REV. E
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