IDT723622L20PF Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT723622L20PF Datasheet PDF : 26 Pages
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IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER-
ATING FREE-AIR TEMPERATURE
Symbol
Parameter
fS Clock Frequency, CLKA or CLKB
tCLK Clock Cycle Time, CLKA or CLKB
tCLKH Pulse Duration, CLKA or CLKB HIGH
tCLKL Pulse Duration, CLKA and CLKB LOW
tDS
tENS
tRSTS
tFSS
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
Setup Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑
Setup Time, RST1 or RST2 LOW before CLKA↑
or CLKB↑(1)
Setup Time, FS0 and FS1 before RST1 and RST2
HIGH
tDH
tENH
tRSTH
tFSH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after
CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
Hold Time, RST1 or RST2 LOW after CLKA↑ or
CLKB↑(1)
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
tSKEW1(2) Skew Time, between CLKA↑ and CLKB↑ for ORA,
ORB, IRA, and IRB
tSKEW2(2) Skew Time, between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, and AFB
723622-15
723632-15
723642-15
Min. Max.
66.7
15
6
6
4
4.5
5
7.5
1
1
4
2
7.5
12
723622-20
723632-20
723642-20
Min. Max.
50
20
8
8
5
5
6
8.5
1
1
4
3
9
16
723622-30
723632-30
723642-30
Min. Max.
33.4
30
10
10
6
6
7
9.5
1
1
5
3
11
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB
cycle.
5.22
8
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