IDT723642L20PQF Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Fabricante

IDT723642L20PQF

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

A0-A35

AEA

Port-A Data

Port-A Almost

-Empty Flag

I/O

I/0

O

(Port A)

AEB

Port-B Almost

O

-Empty Flag (Port B)

AFA

Port-A Almost

O

-Full Flag

(Port A)

AFB

Port-B Almost

O

-Full Flag

(Port B)

B0 - B35 Port-B Data

I/O

CLKA Port-A Clock

I

CLKB Port-B Clock

I

CSA

Port-A Chip

I

Select

CSB

Port-B Chip

I

Select

ENA

Port-A Enable

I

ENB

Port-B Enable

I

FS1,

Flag Offset

I

FS0

Selects

IRA

Input-Ready

O

Flag

(Port A)

IRB

Input-Ready

O

Flag

(Port B)

MBA

Port-A Mailbox I

Select

Description

36-bit bidirectional data port for side A.

Programmable almost-empty flag synchronized to CLKA. It is LOW

when the number of words in FIF02 is less than or equal to the value in the

almost-empty A offset register, X2.

Programmable almost-empty flag synchronzed to CLKB. It is LOW

when the number of words in FIF01 is less than or equal to the value in the

almost-empty B offset register, X1.

Programmable almost-full flag synchronized to CLKA. It is LOW when

the number of empty locations in FIF01 is less than or equal to the value in

the almost-full A offset register, Y1.

Programmable almost-full flag synchronized to CLKB. It is LOW when

the number of empty locations in FIF02 is less than or equal to the value in

the almost-full B offset register, Y2.

36-bit bidirectional data port for side B.

CLKA is a continuous clock that synchronizes all data transfers through port A

and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA

are all synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through port B

and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB

are synchronized to the LOW-to-HIGH transition of CLKB.

CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or

write on port A. The AO-A35 outputs are in the high-impedance state when

CSA is HIGH.

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B. The BO- B35 outputs are in the high-impedance state

when CSB is HIGH.

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B.

The LOW-to-HIGH transition of a FlFO’s reset input latches the values of FSO

and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one

of the three preset values is selected as the offset for the FlFOs almost-full

and almost-empty flags. If both FIFOs are reset simultaneously and both FSO

and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to

FIFO1 almost empty offsets for both FlFOs.

IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is

LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW

when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition

of CLKA after reset.

IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is

LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when

FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of

CLKB after reset.

A HIGH level on MBA chooses a mailbox register for a port-A read or

write operation. When the AO-A35 outputs are active, a HIGH level on MBA

selects data from the mail2 register for output and a LOW level selects FIF02

output-register data for output.

5.22

4

Share Link: