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IDT6198S25D

CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control

Integrated Device Technology 

IDT6198S/L

CMOS STATIC RAM 64K (16K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)

tWC

ADDRESS

OE

CS

WE

DATAOUT

tAW

tAS

tWP

tWR

tWZ (6)

(4)

tOW (6)

(4)

tDW

tDH

DATAIN

DATA VALID

2987 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3)

tWC

ADDRESS

tAW

CS

tAS

tCW

tWR

WE

tDW

tDH

DATAIN

DATA VALID

2987 drw 11

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap ( tWP) of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified tWP.

6.3

7

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