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IDT61298SA

CMOS STATIC RAM 256K (64K x 4-BIT)

Integrated Device Technology 

IDT61298SA

CMOS STATIC RAM 256K (64K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5)

ADDRESS

CS

WE

DATAOUT

DATAIN

tWC

tAW

tAS

tWP (3)

tWR

tWHZ (6)

(4)

tOW (6)

tDW

tDH

DATA VALID

(4)

2971 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5)

ADDRESS

CS

tAS

WE

DATAIN

tWC

tAW

tCW

tWR

tDW

tDH

DATA VALID

2971 drw 09

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to tWHZ + tDW to allow

the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does

not apply and the minimum write pulse is as short as the spectified tWP.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7.1

6

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