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TP2510 Ver la hoja de datos (PDF) - Supertex Inc

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TP2510 Datasheet PDF : 5 Pages
1 2 3 4 5
TP2510
Low Threshold
P-Channel Enhancement Mode
Vertical DMOS FETs
Features
Low threshold — -2.4V max.
High input impedance
Low input capacitance — 125pF max.
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N and P-channel devices
Applications
Logic level interfaces — ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
These low threshold enhancement-mode (normally-off) tran-
sistors utilize a vertical DMOS structure and Supertex’s well-
proven silicon-gate manufacturing process. This combination
produces devices with the power handling capabilities of bipolar
transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, these devices are free from thermal
runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
widerange of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Switching Waveforms and Test Circuit
0V
INPUT
10%
-10V
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tF
0V
OUTPUT
VDD
10%
90%
90%
10%
PULSE
GENERATOR
RGEN
INPUT
D.U.T.
Output
RL
VDD
Thermal Characteristics
Package
ID
continuous
ID
pulsed
Power Dissipation
@ TA = 25OC
θjc
(OC/W)
θjc
(OC/W)
IDR
(mA)
IDRM
(A)
(mA)
(A)
(W)
TO-243AA
-480
-2.5
† I (continuous) is limited by max rated T .
D
j
‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm.
1.6
15
78
-480
-2.5

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