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AD7720

CMOS Sigma-Delta Modulator

Analog Devices 

AD7720

CIRCUIT DESCRIPTION

Sigma-Delta ADC

The AD7720 ADC employs a sigma-delta conversion technique

that converts the analog input into a digital pulse train. The

analog input is continuously sampled by a switched capacitor

modulator at twice the rate of the clock input frequency (2 ×

fMCLK). The digital data that represents the analog input is in

the one’s density of the bit stream at the output of the sigma-

delta modulator. The modulator outputs the bit stream at a data

rate equal to fMCLK.

Due to the high oversampling rate, which spreads the quantiza-

tion noise from 0 to fMCLK/2, the noise energy contained in the

band of interest is reduced (Figure 21a). To reduce the quanti-

zation noise further, a high order modulator is employed to

shape the noise spectrum, so that most of the noise energy is

shifted out of the band of interest (Figure 21b).

QUANTIZATION NOISE

BAND OF INTEREST

a.

fMCLK/2

NOISE SHAPING

BAND OF INTEREST

b.

fMCLK/2

Figure 21. Sigma-Delta ADC

USING THE AD7720

ADC Differential Inputs

The AD7720 uses differential inputs to provide common-mode

noise rejection (i.e., the converted result will correspond to the

differential voltage between the two inputs). The absolute volt-

age on both inputs must lie between AGND and AVDD.

In the unipolar mode, the full-scale input range (VIN(+) –

VIN(–)) is 0 V to VREF. In the bipolar mode configuration, the

full-scale analog input range is ± VREF2/2. The bipolar mode

allows complementary input signals. Alternatively, VIN(–) can

be connected to a dc bias voltage to allow a single-ended input

on VIN(+) equal to VBIAS ± VREF2/2.

Differential Inputs

The analog input to the modulator is a switched capacitor de-

sign. The analog input is converted into charge by highly linear

sampling capacitors. A simplified equivalent circuit diagram of

the analog input is shown in Figure 22. A signal source driving

the analog input must be able to provide the charge onto the

sampling capacitors every half MCLK cycle and settle to the

required accuracy within the next half cycle.

500

VIN(+)

500

VIN(–)

MCLK

A

2pF

B

2pF

A

B

AC

GROUND

AB AB

Figure 22. Analog Input Equivalent Circuit

Since the AD7720 samples the differential voltage across its

analog inputs, low noise performance is attained with an input

circuit that provides low differential mode noise at each input.

The amplifiers used to drive the analog inputs play a critical

role in attaining the high performance available from the AD7720.

When a capacitive load is switched onto the output of an op

amp, the amplitude will momentarily drop. The op amp will try

to correct the situation and, in the process, hits its slew rate

limit. This nonlinear response, which can cause excessive ring-

ing, can lead to distortion. To remedy the situation, a low pass

RC filter can be connected between the amplifier and the input

to the AD7720 as shown in Figure 23. The external capacitor

at each input aids in supplying the current spikes created during

the sampling process. The resistor in this diagram, as well as

creating the pole for the antialiasing, isolates the op amp from

the transient nature of the load.

ANALOG

INPUT

R

VIN(+)

C

R

VIN(–)

C

Figure 23. Simple RC Antialiasing Circuit

The differential input impedance of the AD7720 switched

capacitor input varies as a function of the MCLK frequency,

given by the equation:

ZIN = 109/(8 fMCLK) kΩ

Even though the voltage on the input sampling capacitors may

not have enough time to settle to the accuracy indicated by the

resolution of the AD7720, as long as the sampling capacitor

charging follows the exponential curve of RC circuits, only the

gain accuracy suffers if the input capacitor is switched away too

early.

An alternative circuit configuration for driving the differential

inputs to the AD7720 is shown in Figure 24.

–10–

REV. 0

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