STK12C68-M Ver la hoja de datos (PDF) - Simtek Corporation
Número de pieza
componentes Descripción
Fabricante
STK12C68-M Datasheet PDF : 10 Pages
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STK12C68-M
SRAM MEMORY OPERATION
READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
tELQV
tACS
Chip Enable Access Time
2
tAVAV
3
tAVQVg
tRC
Read Cycle Time
tAA
Address Access Time
4
tGLQV
tOE
Output Enable to Data Valid
5
tAXQX
tOH
Output Hold After Address Change
6
tELQX
7
tEHQZh
tLZ
Chip Enable to Output Active
tHZ
Chip Disable to Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZh
tOHZ
Output Disable to Output Inactive
10
tELICCHe
tPA
Chip Enable to Power Active
11
tEHICCLc,e
tPS
Chip Disable to Power Standby
(VCC = 5.0V ± 10%)d
STK12C68-40M
MIN MAX
STK12C68-45M
MIN MAX
STK12C68-55M
MIN MAX
UNITS
40
45
55
ns
40
45
55
ns
40
45
55
ns
20
25
35
ns
5
5
5
ns
5
5
5
ns
17
20
25
ns
0
0
0
ns
17
20
25
ns
0
0
0
ns
35
45
55
ns
Note c: Bringing E ≥VIH will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.
READ CYCLE #1 f,g
2
tAVAV
ADDRESS
DQ (Data Out)
READ CYCLE #2 f
5
tAXQX
3
tAVQV
DATA VALID
ADDRESS
E
G
DQ (Data Out)
ICC
ACTIVE
STANDBY
10
tELICCH
2
tAVAV
6
tELQX
1
tELQV
4
tGLQV
8
tGLQX
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
4-55
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