IDT723613L30PF Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT723613L30PF
Integrated Device Technology
IDT723613L30PF Datasheet PDF : 29 Pages
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF (SEE FIGURE 4 THROUGH 18)
IDT723613L15 IDT723613L20 IDT723613L30
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑
2
10
2
12
2
15
ns
to B0-B35
tWFF
Propagation Delay Time, CLKA↑ to FF
2
10
2
12
2
15
ns
tREF
Propagation Delay Time, CLKB↑ to EF
2
10
2
12
2
15
ns
tPAE
Propagation Delay Time, CLKB↑ to AE
2
10
2
12
2
15
ns
tPAF
Propagation Delay Time, CLKA↑ to AF
2
10
2
12
2
15
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW 1
9
1
12
1
15
ns
or MBF2 HIGH and CLKB↑ to MBF2 LOW or
MBF1 HIGH
tPMR
tPPE(3)
Propagation Delay Time, CLKA↑ to B0-B35(1)
and CLKB↑ to A0-A35(2)
Propagation delay time, CLKB↑ to PEFB
3
11
3
12
3
15
ns
2
11
2
12
2
13
ns
tMDV
Propagation Delay Time, SIZ1, SIZ0 to
1
11
1 11.5 1
12
ns
B0-B35 valid
tPDPE Propagation Delay Time, A0-A35 valid to PEFA 3
10
3
11
3
13
ns
valid; B0-B35 valid to PEFB valid
tPOPE Propagation Delay Time, ODD/EVEN to PEFA
3
11
3
12
3
14
ns
and PEFB
tPOPB(4) Propagation Delay Time, ODD/EVEN to parity
2
12
2
13
2
15
ns
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
tPEPE Propagation Delay Time, CSA, ENA, W/RA,
1
11
1
12
1
14
ns
MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1,
SIZ0, or PGB to PEFB
tPEPB(4) Propagation Delay Time, CSA, ENA, W/RA,
3
12
3
13
3
14
ns
MBA, or PGA to parity bits (A8, A17, A26, A35);
CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity
bits (B8, B17, B26, B35)
tRSF
Propagation Delay Time, RST to AE, EF
LOW and AF, MBF1, MBF2 HIGH
1
15
1
20
1
25
ns
tEN
Enable Time, CSA and W/RA LOW to A0-A35
2
10
2
12
2
14
ns
active and CSB LOW and W/RB HIGH to
B0-B35 active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35
1
8
1
9
1
11
ns
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active.
3. Only applies when a new port-B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.
8
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