AD7769 Ver la hoja de datos (PDF) - Analog Devices
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Fabricante
AD7769 Datasheet PDF : 16 Pages
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AD7769
TIMING CHARACTERISTICS1, 2 (VCC = +5 V ؎ 5%; VDD = +12 V ؎ 10%; AGND [ADC] = AGND [DAC] = DGND = 0 V.
For ADC and DAC, VBIAS = +5 V, VSWING = +2.5 V.)
Parameter
Label
Limit at Limit at
+25؇C TMIN, TMAX Units
Test Conditions/Comments
ADC /DAC CONTROL TIMING
CS to WR Setup Time
CS to WR Hold Time
ADC/DAC to WR Setup Time
ADC/DAC to WR Hold Time
CHA/CHB to WR Setup Time
CHA/CHB to WR Hold Time
WR Pulse Width
t1
0
0
t2
0
0
t3
0
0
t4
0
0
t5
0
0
t6
0
0
t7
80
80
ns min
ns min
ns
ns min
ns min
ns min
ns min
ADC CONVERSION TIMING
Using External Clock
WR to INT Low Delay
Using Internal Clock
WR to INT Low Delay
WR to INT High Delay
WR to Data Valid Delay3
t8
2.6
2.6
t8
1.9/3.0 1.9/3.0
t9
85
85
t9
120
120
t10
t8+70 t8+70
t10
t8+110 t8+110
µs max
µs min/max
ns max
ns max
ns max
ns max
Load Circuit of Figure 3, CL = 20 pF
Load Circuit of Figure 3, CL = 20 pF
Typically 2.5 µs
Load Circuit of Figure 3, CL = 20 pF
Load Circuit of Figure 3, CL = 100 pF
Load Circuit of Figure 1, CL = 20 pF
Load Circuit of Figure 1, CL = 100 pF
ADC READ TIMING
CS to RD Setup Time
t11
0
0
CS to RD Hold Mode
t12
0
0
RD to Data Valid Delay3
t13
15/65 15/65
t13
30/100 30/100
Bus Relinquish Time after RD High4
t14
15/65 15/65
RD to INT High Delay
t15
80
80
RD Pulse Width
t15
110
110
t16
t13
t13
ns min
ns min
ns min/max
ns min/max
ns min/max
ns max
ns max
ns min
Load Circuit of Figure 1, CL = 20 pF
Load Circuit of Figure 1, CL = 100 pF
Load Circuit of Figure 2
Load Circuit of Figure 3, CL = 20 pF
Load Circuit of Figure 3, CL = 100 pF
Determined by t13
DAC WRITE TIMING
Data Valid to WR Setup Time
Data Valid to WR Hold Time
WR to DAC Output Settling Time
t17
65
65
t18
15
20
t19
4
4
ns nıin
ns min
µs max
Load Circuit of Figure 4
NOTES
1See Figures 11, 12 and 13.
2Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3t10 and t13 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t14 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Bus Relinquish Time Test
Figure 3. Load Circuit for RD and WR to INT Delay Test
Figure 4. Load Circuit for DAC Settling Time Test
–4–
REV. A
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