M48Z09 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M48Z09

CMOS 8K x 8 ZEROPOWER SRAM

STMicroelectronics 

M48Z09, M48Z19

WRITE MODE

The M48Z09,19 is in the Write Mode whenever W,

E1, and E2 are active. The start of a write is refer-

enced from the latter occurring falling edge of W or

E1, or the rising edge of E2. A write is terminated

by the earlier rising edge of W or E1, or the falling

edge of E2. The addresses must be held valid

throughout the cycle. E1 or W must return high or

E2 low for minimum of tE1HAX or tE2LAX from Chip

Enable or tWHAX from Write Enable prior to the

initiation of another read or write cycle. Data-in

must be valid tDVWH prior to the end of write and

remain valid for tWHDX afterward. G should be kept

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E1 and G and a high on E2, a low on W will

disable the outputs tWLQZ after W falls.

DATA RETENTION MODE

With valid VCC applied, the M48Z09,19 operates as

a conventional BYTEWIDE™ static RAM. Should

the supply voltage decay, the RAM will automat-

ically power-fail deselect, write protecting itself

when VCC falls within the VPFD(max), VPFD(min)

window. All outputs become high impedance, and

all inputs are treated as "don’t care."

Note: A power failure during a write cycle may

corrupt data at the currently addressed location, but

does not jeopardize the rest of the RAM’s content.

At voltages below VPFD(min), the user can be as-

sured the memory will be in a write protected state,

provided the VCC fall time is not less than tF. The

M48Z09,19 may respond to transient noise spikes

on VCC that reach into the deselect window during

the time the device is sampling VCC. Therefore,

decoupling of the power supply lines is recom-

mended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48Z09,19 for

an accumulated period of at least 10 years when

VCC is less than VSO. As system power returns and

VCC rises above VSO, the battery is disconnected,

and the power supply is switched to external VCC.

Write protection continues until VCC reaches

VPFD(min). E1 should be kept high or E2 low as

VCC rises past VPFD(min) to prevent inadvertent

write cycles prior to processor stabilization. Normal

RAM operation can resume tREC after VCC exceeds

VPFD(max).

POWER FAIL INTERRUPT PIN

The M48Z09,19 continuously monitors VCC. When

VCC falls to the power-fail detect trip point, an

interrupt is immediately generated. An internal

clock provides a delay of between 10µs and 40µs

before automatically deselecting the M48Z09,19.

The INT pin is an open drain output and requires

an external pull up resistor, even if the interrupt

output function is not being used.

SYSTEM BATTERY LIFE

The useful life of the battery in the M48Z09,19 is

expected to ultimately come to an end for one of

two reasons: either because it has been discharged

while providing current to the RAM in the battery

back-up mode, or because the effects of aging

render the cell useless before it can actually be

completely discharged. The two effects are virtually

unrelated allowing discharge, or Capacity Con-

sumption, and the effects of aging, or Storage Life,

to be treated as two independent but simultaneous

mechanisms. The earlier occurring failure mecha-

nism defines the battery system life of the

M48Z09,19.

Cell Storage Life

Storage life is primarily a function of temperature.

Figure 9 illustrates the approximate storage life of

the M48Z09,19 battery over temperature. The re-

sults in Figure 9 are derived from temperature

accelerated life test studies performed at SGS-

THOMSON. For the purpose of the testing, a cell

failure is defined as the inability of a cell stabilized

at 25°C to produce a 2.4V closed circuit voltage

across a 250 kΩ load resistor. The two lines, t1%

and t50%, represent different failure rate distribu-

tions for the cell’s storage life. At 70°C, for example,

the t1% line indicates that an M48Z09,19 has a 1%

chance of having a battery failure 28 years into its

life while the t50% shows the part has a 50% chance

of failure at the 50 year mark. The t1% line repre-

sents the practical onset of wear out and can be

considered the worst case Storage Life for the cell.

The t50% can be considered the normal or average

life.

9/13

Share Link: