CDP1826C Ver la hoja de datos (PDF) - Intersil

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componentes Descripción

Fabricante

CDP1826C

CMOS 64-Word x 8-Bit Static RAM

Intersil 

CDP1826C

Signal Descriptions

A0 - A4, CS/A5 (Address Inputs): These inputs must be

stable prior to a write operation, but may change asynchro-

nously during Read operations.

In an 1800 system, the multiplexed high-order address bit at

pin CS/A5 can be latched at the end of TPA. A high level will

provide a valid chip select for the CDP1826C. The low-order

address bit which appears after TPA is used for data word

selection. In non-1800 systems, TPA can be tied high to dis-

able the latch and allow the CS/A5 pin to function as a nor-

mal address input.

BUS 0 - BUS 7: 8-bit three-state common input/output data

bus.

TPA: High-order address strobe input. The high-order

address bit at input CS/A5 is latched on the high-to-low tran-

sition of the TPA input. Tie TPA high to disable the CS/A5

latch feature.

CS1, CS2 (Chip Selector): Either chip select (CS1 or CS2),

when not valid, powers down the chip, disables READ and

WRITE functions, and gates off the address and output buffers.

MRD, MWR: Read and Write control signals. MWR over-

rides MRD, allowing the CDP1826C to be controlled from a

single R/W line.

CEO (Chip Enable Output): Allows daisy chaining to addi-

tional memories. CEO is high whenever the CDP1826C is

selected. CEO is only active (low) for a Read cycle with the

CDP1826C deselected and the MRD input low.

VDD, VSS: Power supply connections.

A0

A1

A2

A3

A4

CS/A5

TPA

CS1

CS2

MWR

MRD

INPUT

ADDRESS

BUFFERS

XY

DECODE

64 x 8

MATRIX

INPUT/OUTPUT

DATA

BUFFERS

AND

CONTROL

D

Q

C

FIGURE 2. FUNCTIONAL DIAGRAM

BUS 0

BUS 1

BUS 2

BUS 3

BUS 4

BUS 5

BUS 6

BUS 7

CEO

6-50

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