LG1600FXH0553 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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LG1600FXH0553 Datasheet PDF : 20 Pages
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Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Theory of Operation (continued)
Consequently, the timing information that is present in
the data needs to be extracted and a decision as to the
value of each bit must be made. Both timing instant and
decision levels are critical, since the economics of data
transmission dictate the largest distance possible
between transmitter and receiver. A practically closed
data eye can therefore be expected at the output of the
receiver, allowing only a small decision window.
An added complication in nonreturn-to-zero (NRZ) sys-
tems is the absence of clock component in the data
signal itself. Practical clock recovery circuits have used
a combination of nonlinear processing to extract a
spectral component at the clock frequency and narrow-
band filtering using a SAW filter or dielectric resonator.
The relative bandwidth of such a filter must be on the
order of a few tenths of a percent to minimize the data
pattern dependence of the resulting clock. Temperature
behavior of the passband characteristics, such as
group delay, must be tightly matched to that of the data
path. These extreme requirements make such a dis-
crete design very difficult to manufacture at Gbits/s
data rates.
The LG1600FXH clock and data regenerator relies on
phase-lock loop techniques, rather than passive filter-
ing. The filter properties of a PLL are determined at low
frequencies where parasitic elements play only a minor
roll and stability is easily maintained. Furthermore, the
reference frequency is determined by the data rate
itself, rather than by the physical properties of a band-
pass filter.
Although PLLs can eliminate some of the shortcomings
of passive bandpass filters used in clock recovery cir-
cuits, care was taken in the design of the LG1600FXH
to preserve desired properties such as linearity of the
jitter characteristics. A linear jitter transfer makes it a lot
easier for the system designer to predict the overall
performance of a link.
As a result, the architecture chosen for the device is not
basically different from the conventional clock recovery
circuit. A transition detector extracts a pulse train from
the incoming data signal which is used as a reference
signal for a PLL. The transition pulse train can be seen
as a clock signal that is modulated with the instanta-
neous transition density of the data signal. The PLL
locks onto the frequency and phase of this pulse train
and freewheels during times when transitions are
absent. The LG1600FXH features dual phase detec-
tors; one driven by an in-phase clock which is also driv-
ing the decision circuit flip-flop, the other is driven by a
quadrature clock. The phase detectors produce a zero
output when their respective clocks are centered with
respect to the transition pulses.
DATA
CIRCULATOR
TO FLIP-FLOP
TRANSITION
PULSE
PDI
DELAYED
DATA
PDQ
0°
FROM
VCO
90°
STUB
LOGIC
FPD OUT
12-3226(F)r.3
Figure 3. Frequency and Phase Detector
For a transition pulse of half the width of the bit period,
the timing diagram of Figure 4 shows how the in-phase
clock ends up in the center of the data eye when the
quadrature-phase detector output is forced to zero by
the loop. The (patented) transition detector is com-
prised of an (active) circulator, a shorted stub, and an
exclusive-OR gate. The circulator/stub combination
produces a delayed version of the data. A transition at
the input of the circuit results in an output pulse from
the exclusive-OR gate whose width equals the return
delay of the stub. The stub is tuned for a given bit rate
and can be adjusted so that the in-phase clock is
exactly centered in the error-free phase range of the
retiming flip-flop.
1/2 T
DATA
DELAYED
DATA
T
1/4 T
TRANSITION
PULSE
0°
CLOCK
90°
CLOCK
Figure 4. Timing Diagram
12-3227(F)r.2
Lucent Technologies Inc.
3
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