Tripath Technology, Inc. - Technical Information
TPS1035 POWER STAGE PIN DESCRIPTIONS
Pin
Function
Description
1
INPUT
Input pin for power stage.
2
VDD
Positive supply pin.
3
OUTPUT
Output pin.
4
PGND
Power Ground pin.
5
VBOOT
Bootstrapped voltage to supply drive to gate of high-side output MOSFET.
6
SLEEP
Sleep Input pin. When set to logic level high, sleep mode is enabled. When set
to logic level low (grounded), sleep mode is disabled.
7
BYPASS
Bypass pin for the gate drive power supply. The gate drive for the output mosfets
are internally generated from VDD. This pin should be connected to ground
through a 1.0uF or larger capacitor. This pin must be connected to the Fault pin
(pin 8) through a 27kΩ resistor.
8
FAULT
Fault Output pin. During normal operation this pin is high. If an overcurrent or
over temperature condition is detected the fault pin will become low. This pin
must be connected to the Bypass pin (pin 7) through a 27kΩ resistor.
TPS1035 POWER STAGE PINOUT
(Top view with heat slug down)
8-pin SOIC with Heatslug
(Top View)
INPUT
1
VDD
2
OUTPUT
3
PGND
4
8
FAULT
7
BYPASS
6
SLEEP
5
VBOOT
6
TK2070 – MC/2.1/10-03