M80C51FB Ver la hoja de datos (PDF) - Intel
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M80C51FB Datasheet PDF : 12 Pages
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M80C51FB
D C CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol
Parameter
Min
Max Unit
Test Conditions
VOH1
IIL
Output High Voltage
(Port 0 in External Bus Mode
ALE PSEN)
Logical 0 Input Current
(Ports 1 2 and 3)
VCCb0 3
VCCb0 7
VCCb1 5
b75
V
IOH e b200 mA (Note 2)
V
IOH e b3 2 mA
V
IOH e b7 0 mA (Note 4)
mA VIN e 0 45V
ILI
Input leakage Current (Port 0)
ITL
Logical 1 to 0 Transition Current
(Ports 1 2 and 3)
g10
mA 0 45V k VIN k VCC
b750 mA VIN e 2V
RRST
RST Pulldown Resistor
40
225
KX
CIO
Pin Capacitance
10
pF
1 MHz 25 C
ICC
Power Supply Current
Active Mode 16 MHz
Idle Mode 16 MHz
Power Down Mode 16 MHz
(Note 3)
45
mA
15
mA
130
mA
NOTES
1 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to
0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE
signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch
with a Schmitt Trigger Strobe input
2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC b 0 3 specification when
the address lines are stabilizing
3 See Figures 5 – 8 for load circuits Minimum VCC for Power Down is 2V
4 Care must be taken not to exceed the maximum allowable power dissipation
5 Under steady state (non-transient) conditions IOL must be externally limited as follows
Maximum IOL per port pin
10mA
Maximum IOL per 8-bit port
Port 0 26 mA
Ports 1 2 and 3 15 mA
Maximum total IOL for all output pins
71 mA
If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater
than the listed test conditions
All other pins disconnected
TCLCH e TCHCL e 5 ns
271172 –6
Figure 5 ICC Load Circuit Active Mode
All other pins disconnected
TCLCH e TCHCL e 5 ns
271172 – 7
Figure 6 ICC Load Circuit Idle Mode
7
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