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TDA9109SN

LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

STMicroelectronics 

TDA9109/SN

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC

VDD

VIN

VESD

Tstg

Tj

Toper

Parameter

Supply Voltage (Pin 29)

Supply Voltage (Pin 32)

Max Voltage on Pin 4

Pin 5

Pins 6, 7, 8, 14, 15, 16, 20, 22

Pins 9, 10, 18, 23, 24, 25, 26, 28

Pins 1, 2, 3, 30, 31

ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ

EIAJ Norm, 200pF Discharge through 0Ω

Storage Temperature

Junction Temperature

Operating Temperature

Value

13.5

5.7

4.0

6.4

8.0

VCC

VDD

2

300

-40, +150

+150

0, +70

Unit

V

V

V

V

V

V

V

kV

V

oC

oC

oC

THERMAL DATA

Symbol

Parameter

Rth (j-a) Junction-Ambient Thermal Resistance

Max.

Value

65

Unit

oC/W

SYNC PROCESSOR

Operating Conditions (VDD = 5V, Tamb = 25oC)

Symbol

HsVR

MinD

Mduty

Parameter

Voltage on H/HVIN Input

Minimum Horizontal Input Pulses Duration

Maximum Horizontal Input Signal Duty Cycle

Test Conditions

Pin 1

Pin 1

Pin 1

VsVR Voltage on VSYNCIN

Pin 2

VSW Minimum Vertical Sync Pulse Width

Pin 2

VSmD Maximum Vertical Sync Input Duty Cycle

Pin 2

VextM Maximum Vertical Sync Width on TTL H/Vcomposite Pin 1

IHLOCKOUT Sink and Source Current

Pin3

Electrical Characteristics (VDD = 5V, Tamb = 25oC)

Symbol

Parameter

Test Conditions

VINTH

RIN

TfrOut

VHlock

VoutT

Horizontal and Vertical Input Logic Level

(Pins 1, 2)

Horizontal and Vertical Pull-Up Resistor

Fall and Rise Time, Output CMOS Buffer

Horizontal 1st PLL Lock Output Status (Pin 3)

Extracted Vsync Integration Time (% of TH)

on H/V Composite (see Note 1)

Low Level

High Level

Pins 1, 2

Pin 3, COUT = 20pF

Locked, ILOCKOUT = -250µA

Unlocked, ILOCKOUT = +250µA

C0 = 820pF

Note 1 : TH is the horizontal period.

Min.

0

0.7

0

5

Min.

2.2

4.4

26

Typ.

Typ.

200

0

5

35

Max.

5

25

5

15

750

250

Max.

0.8

200

0.5

Unit

V

µs

%

V

µs

%

µs

µA

Unit

V

V

kΩ

ns

V

V

%

I2C READ/WRITE (see Note 2)

Electrical Characteristics (VDD = 5V,Tamb = 25oC)

Symbol

I2C PROCESSOR

Parameter

Fscl Maximum Clock Frequency

Tlow Low period of the SCL Clock

Thigh High period of the SCL Clock

Vinth SDA and SCL Input Threshold

VACK Acknowledge Output Voltage on SDA input with 3mA

Note 2 : See also I2C Table Control and I2C Sub Address Control.

Test Conditions Min. Typ. Max. Unit

Pin 30

Pin 30

Pin 30

Pins 30,31

Pin 31

400 kHz

1.3

µs

0.6

µs

2.2

V

0.4 V

6/30

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