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TDA9965

12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras

Philips Electronics 

Philips Semiconductors

12-bit, 5.0 V, 30 Msps analog-to-digital

interface for CCD cameras

Product specification

TDA9965

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

DNL

differential non linearity

ramp input

td(s)

sampling delay

see Fig.5

Total chain characteristics (CTH + PGA + ADC)

−

±0.5

−

−

td(SHD-CLKADC) delay between

SHD and CLKADC

th(SHD-CLKADC) SHD hold time compared to

CLKADC

Ntot(rms)

total noise from CTH input to

ADC output (RMS value)

OCCD(max)

maximum offset voltage

between CCD floating level

and CCD dark pixel level

Vn(i)(eq)(rms)

equivalent input noise

(RMS value)

Digital outputs (fpix = 30 MHz; CL = 10 pF)

VOH

HIGH-level output voltage

VOL

LOW-level output voltage

th(o)

output hold time

td(o)

output delay

Serial interface

Vi(IN) = 1000 mV;

transition (99%) in 1 pixel;

code fco(CTH) = 0000;

code GPGA = 128; see Fig.5

Vi(IN) = 32 mV;

transition (99%) in 1 pixel;

code fco(CTH) = 0000;

code GPGA = 767; see Fig.5

GPGA = 0 dB;

code fco(CTH) = 0000

GPGA = 30 dB;

code fco(CTH) = 0000; note 1

see Fig.11

GPGA = 30 dB;

code fco(CTH) = 0000; note 1

IOH = −1 mA

IOL = 1 mA

see Fig.5

VCCO = 5.25 V

VCCO = 3 V

VCCO = 2.5 V

−

13

−

0

−

0.85

−

6

−200

−

−

90

VCCO − 0.5 −

0

−

10

−

−

20

−

26

−

30

fSCLK(max)

maximum clock frequency of

serial interface

5

−

Note

1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.

MAX. UNIT

±0.9 LSB

5

ns

−

ns

−

ns

−

LSB

−

LSB

+200 mV

−

µV

VCCO V

0.5 V

−

ns

25

ns

31

ns

35

ns

−

MHz

2004 Jul 05

9

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