TDA9910 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
TDA9910
Philips Electronics
TDA9910 Datasheet PDF : 21 Pages
| |||
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test [1] Min
Typ
Max
Unit
IIL
LOW-level input current VIL = 0.8 V
IIH
HIGH-level input current VIH = 2.0 V
Digital inputs: pins DEL0 and DEL1
-
5
-
µA
-
5
-
µA
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IIL
LOW-level input current VIL = 0.8 V
IIH
HIGH-level input current VIH = 2.0 V
Voltage controlled regulator output: pin CMADC
DGND
-
0.7 × VCCD -
-
80
-
80
0.3 × VCCD V
VCCD
V
-
µA
-
µA
Vo(CM) common mode output
voltage
IL = 0 mA
IL = 2 mA
Reference voltage input: pin FSIN [3]
-
VCCA − 1.88 -
V
-
VCCA − 1.91 -
V
VFSIN full-scale fixed voltage
-
VCCA − 1.84 -
V
IFSIN
input current
-
1
-
µA
Vi(p-p) input voltage
see Figure 5;
1.5
1.9
2.0
V
(peak-to-peak value)
Vi = VIN − VINN;
Vi(CM) = VCCA − 1.91 V
Full-scale voltage controlled regulator output: pin FSOUT
Vo(ref)
1.9 V full-scale output
voltage
IL = IFSIN
IL = 2 mA
Digital outputs: pins D11 to D0, IR and CCS
-
VCCA − 1.84 -
V
-
VCCA − 1.87 -
V
Output levels
VOL
LOW-level output voltage IOL = 2 mA
VOH
HIGH-level output voltage IOH = −0.4 mA
IOZ
output current in 3-state output level between
0.5 V and VCCO
Timing [4]
DGND
-
VCCO − 0.5 -
−20
1
DGND + 0.5 V
VCCO
V
+20
µA
td(s)
sampling delay time
th(o)
output hold time
td(o)
output delay time
3-state output delay
CL = 10 pF
CL = 10 pF
CL = 10 pF
-
0.2
-
ns
-
4
-
ns
-
5
-
ns
tdZH
enable HIGH
tdZL
enable LOW
tdHZ
disable HIGH
tdLZ
disable LOW
Clock timing inputs: pins CLK and CLKN
-
3
-
ns
-
5
-
ns
-
8
-
ns
-
5
-
ns
fCLK(min) minimum clock frequency
fCLK(max) maximum clock frequency duty cycle 45 % to
65 %
-
-
8
80
-
-
Msample/s
Msample/s
tCLKH
tCLKL
clock pulse width HIGH
clock pulse width LOW
fi = 175 MHz
fi = 175 MHz
5.6
-
-
ns
5.6
-
-
ns
9397 750 14418
Objective data sheet
Rev. 02 — 9 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7 of 21
Share Link: