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TDA9855

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled BTSC stereo/SAP

decoder and audio processor

Product specification

TDA9855

handbook, halfpage

TL 1

52 TR

B1L 2

51 B1R

B2L 3

50 B2R

OUTS 4

49 SW

MAD 5

48 n.c.

OUTL 6

47 OUTR

LDL 7

46 LDR

VIL 8

45 VIR

EOL 9

44 EOR

CAV 10

Vref 11

LIL 12

43 CPS1

42 CPS2

41 LIR

AVL 13

40 AVR

TDA9855

SOL 14

39 SOR

LOL 15

38 LOR

CTW 16

CTS 17

CW 18

Cs 19

VEO 20

VEI 21

CNR 22

CM 23

CDEC 24

GND 25

SDA 26

37 CSS

36 CMO

35 CER

34 CADJ

33 CPH

32 CP2

31 CP1

30 VCAP

29 COMP

28 VCC

27 SCL

MHA835

Fig.3 Pin configuration (SDIP version).

FUNCTIONAL DESCRIPTION

Decoder

INPUT LEVEL ADJUSTMENT

The composite input signal is fed to the input level

adjustment stage. In order to compensate tolerances of

the FM demodulator which supplied the composite input

signal, the TDA9855 provides an input level adjustment

stage. The control range is from −3.5 to +4.0 dB in steps of

0.5 dB. The subaddress control 3 of Tables 5 and 6 and

the level adjust setting of Table 22 allows an optimum

signal adjustment during the set alignment in the

production line. This value has to be stored in a

non-volatile memory. The maximum input signal voltage is

2 V (RMS).

STEREO DECODER

The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise

above 125 kHz. The composite signal is then fed into a

pilot detector/pilot cancellation circuit and into the MPX

demodulator. The main L + R signal passes a 75 µs fixed

de-emphasis filter and is fed into the dematrix circuit.

The decoded sub-signal L − R is sent to the stereo/SAP

switch. To generate the pilot signal the stereo demodulator

uses a PLL circuit including a ceramic resonator.

The stereo channel separation can be adjusted by an

automatic procedure or manually. For a detailed

description see Section “Adjustment procedure”.

The stereo identification can be read by the I2C-bus

(see Table 2). Two different pilot thresholds can be

selected via the I2C-bus (see Table 24).

SAP DEMODULATOR

The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit

through a 5fH (fH = horizontal frequency) band-pass filter.

The demodulator level is automatically controlled.

The SAP demodulator includes internal noise and field

strength detectors that mute the SAP output in the event of

insufficient signal conditions. The SAP identification signal

can be read by the I2C-bus (see Table 2).

SWITCH

The stereo/SAP switch feeds either the L − R signal or the

SAP demodulator output signal via the internal dbx noise

reduction circuit to the dematrix/line out select circuit.

Table 21 shows the different switch modes provided at the

output pins LOR and LOL.

1997 Nov 04

9

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