TDA9853 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
TDA9853 Datasheet PDF : 28 Pages
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Philips Semiconductors
I2C-bus controlled economic BTSC stereo
decoder and audio processor
Product specification
TDA9853H
handbook, full pagewidth
n.c. 1
CP2 2
CP1 3
COMP 4
CMO 5
CSS 6
RFR 7
LIL 8
LOL 9
VIL 10
VAL 11
TDA9853H
33 FDO
32 BPU
31 CW
30 TW
29 CAV
28 VCAP
27 Vref
26 LIR
25 LOR
24 VIR
23 VAR
MHB790
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Stereo decoder
The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator. The
main L + R signal passes a 75 µs fixed de-emphasis filter
and is fed into the dematrix circuit. The decoded sub-signal
L − R is applied to the Volume Controlled Amplifier (VCA)
circuit. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
Mode selection
The L − R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via
the I2C-bus (see Table 9).
The dematrix outputs can be muted via the I2C-bus
(see Table 14).
Automatic volume level control
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range between 0.1 to 1.1 V (RMS). The
circuit adjusts variations in modulation during broadcasting
and because of changes in the programme material; this
function can be switched off. To avoid audible plops during
the permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay times can be changed via the I2C-bus.
Integrated filters
The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled by the filter reference circuit via
the external resistor R4.
2000 Dec 11
7
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