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80C196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

BHE#

BREQ#

CLKOUT

CS5#:0

EA#

12

Table 8. Pin Descriptions (Continued)

Type

O

O

O

O

I

Description

Byte High Enable

The chip configuration register 0 (CCR0) determines whether this

pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#;

CCR0.2=0 selects WRH#.

During 16-bit bus cycles, this active-low output signal is asserted for

word reads and writes and high-byte reads and writes to external

memory. BHE# indicates that valid data is being transferred over

the upper half of the system data bus. Use BHE#, in conjunction

with A0, to determine which memory byte is being transferred over

the system bus:

BHE# A0 Byte(s) Accessed

0

0 both bytes

0

1 high byte only

1

0 low byte only

Bus Request

This active-low output signal is asserted during a hold cycle when

the bus controller has a pending external memory cycle.

The device can assert BREQ# at the same time as or after it asserts

HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#

is removed.

You must enable the bus-hold protocol before using this signal.

Clock Output

Output of the internal clock generator. The CLKOUT frequency is ½

the internal operating frequency (FXTAL1). CLKOUT has a 50% duty

cycle.

Chip-select Lines 0–5

The active-low output CSx# is asserted during an external memory

cycle when the address to be accessed is in the range programmed

for chip select x. If the external memory address is outside the

range assigned to the six chip selects, no chip-select output is

asserted and the bus configuration defaults to the CS5# values.

Immediately following reset, CS0# is automatically assigned to the

range FF2000–FF20FFH (F2000–F20FFH if external).

External Access

This input determines whether memory accesses to special-

purpose and program memory partitions (FF2000–FF2FFFH) are

directed to internal or external memory. These accesses are

directed to internal memory if EA# is held high and to external

memory if EA# is held low. For an access to any other memory

location, the value of EA# is irrelevant.

EA# is not latched and can be switched dynamically during normal

operating mode. Be sure to thoroughly consider the issues, such as

different access times for internal and external memory, before

using this dynamic switching capability.

On devices with no internal nonvolatile memory, always connect

EA# to VSS.

Multiplexed

with

WRH#

P2.3

P2.7

P3.5:0

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