TC5565 Ver la hoja de datos (PDF) - Toshiba
Número de pieza
componentes Descripción
Fabricante
TC5565 Datasheet PDF : 9 Pages
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TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 2 :
In \CE1 controlled data retention mode, minimum standby current mode is achieved under the condition Of CE2<= O.2V Or
CE2>= VDD -0.2V.
3 : If the VIH of \CE1 is 2.2V in operation, IDDS1 current flows during the period that the VDD voltage is going down from 4.5V to
2.4V,
4 ; In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V.
DEVICE INFORMATION
The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous.
Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient.
Therefore the peak current flows only after row address change, as shown in the following figure.
This peak current may induce the noise on VDD /GND lines. Thus the use of about 0.1uF decoupling capacitor for every device is
recommended to eliminate such noise.
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