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TC7662B Datasheet PDF : 11 Pages
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CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
TC7662B
Paralleling Devices
Changing the TC7662B Oscillator Frequency
Any number of TC7662B voltage converters may be
paralleled to reduce output resistance (Figure 5). The reser-
voir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
ROUT =
ROUT (of TC7662B)
n (number of devices)
V+
1
8
2
7
C1
TC7662B
3
6
1
8
2
7
RL
4
"1"
5
C1
3 TC7662B 6
4
"n"
5
+ C2
Figure 5. Paralleling Devices
Cascading Devices
The TC7662B may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output voltage
is defined by:
VOUT = – n(VIN)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be ap-
proximately the weighted sum of the individual TC7662B
ROUT values.
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by one of several methods described
below:
By connecting the BOOSTPin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence the
oscillator frequency is increased by approximately 3-1/2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount appli-
cations where capacitor size and cost are critical. Smaller
capacitors, e.g., 0.1µF, can be used in conjunction with the
Boost Pin in order to achieve similar output currents com-
pared to the device free running with C1 = C2 = 1µF or 10µF.
(Refer to graph of Output Source Resistance as a Function
of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock as shown
in Figure 7. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock fre-
quency using TTL logic, the addition of a 10kΩ pullup
resistor to V+ supply is required. Note that the pump fre-
quency with external clocking, as with internal clocking, will
be 1/2 of the clock frequency. Output transitions occur on the
positive-going edge of the clock.
+
10µF
1
8
2
7
3 TC7662B 6
4
5
V+
1 kΩ
V+
CMOS
GATE
VOUT
10µF
+
Figure 7. External Clocking
+
10µF
V+
1
8
2
7
3 TC7662B 6
4
"1"
5
+
10µF
*VOUT = –nV+
10µF
1
8
2
7
3 TC7662B 6
4 "n" 5
VOUT
+ 10µF
Figure 6. Cascading Devices for Increased Output Voltage
© 2001 Microchip Technology Inc. DS21469A
It is also possible to increase the conversion efficiency
of the TC7662B at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 8. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C1 and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (Osc) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (multiple of 10), and thereby necessitate a corre-
sponding increase in the value of C1 and C2 (from 10µF to
100µF).
5
TC7662B-8 9/11/96
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