CXD1257AR Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD1257AR

CCD Camera Timing Generator

Sony Semiconductor 

CXD1257AR

3-2. serial input (PS = L)

For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2

(Pin 9) pins as SMD1 and SMD2 (shutter mode control).

In this case, control by SMD1 and SMD2 pins is invalid.

ED1 (CLK)

ED2 (DATA)

D0

D1

D2

D3

D4

D5

D6

D7

D8 SMD1 SMD2 Dummy

ED0 (STB)

ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0.

–8–

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