CXD1257AR Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza

componentes Descripción

Fabricante

CXD1257AR

CCD Camera Timing Generator

Sony Semiconductor 

CXD1257AR

2. Changes in I/O Signals in Each Mode

Symbol Pin No.

Analog color

Digital color 1

Digital color 2

GM

55

L

H

H

D2

12

L

L

L

TEST2 36

L

L

H

XSP1

Color separation

41 sample-and-hold

pulse output

Halted at High

Color separation

sample-and-hold

pulse output

XSP2

Color separation

42 sample-and-hold

pulse output

Halted at High

Color separation

sample-and-hold

pulse output

XSH1

Switching sample-

43 and-hold pulse

Halted at Low

output

Switching sample-

and-hold pulse

output

XSH2

Switching sample-

44 and-hold pulse

Halted at Low

output

Switching sample-

and-hold pulse

output

XDL1

45 Delay line clock

Halted at High

Halted at High

XDL2

46 Delay line clock

Halted at Low

Halted at Low

BFG

47 Burst flag gate

pulse output

Burst flag gate

Burst flag gate

pulse output

pulse output

(normally not used) (normally not used)

CLP2

CLP3

Standby control input Standby control input

49

Clamp pulse output

Low: Standby

High: Normal

Low: Standby

High: Normal

operation

operation

Standby control∗

Standby control∗

Low: All circuits

Low: All circuits

halted for

halted for

50 Clamp pulse output

standby mode

standby mode

High: Only CL

High: Only CL

output for

output for

standby mode

standby mode

ID

53 Line identification Line identification Line identification

output

output

output

∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low.

(Mode combinations other than those shown above cannot be used.)

Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG,

XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4,

PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before

standby.

–6–

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