T431616D Ver la hoja de datos (PDF) - Taiwan Memory Technology

Número de pieza

componentes Descripción

Fabricante

T431616D

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616D/E

4 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after the read

operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.)

+ burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge

function is ignored.

5 Write command

(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active row in an

active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write

bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data

elements will be registered on each successive positive clock edge (refer to the following figure). The DQs

remain with high-impedance at the end of the burst unless another command is initiated. The burst length and

burst sequence are determined by the mode register, which is already programmed. A full-page burst will

continue until terminated (at the end of the page it will wrap to column 0 and continue).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

NOP

WRITE A

NOP

NOP

NOP

NOP

NOP

NOP

NOP

DQ0 - DQ3

DIN A0

DIN A1

DIN A2

DIN A3

don't care

The first data element and the write

are registered on the same clock edge.

Extra data is masked.

Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)

A write burst without the auto precharge function may be interrupted by a subsequent Write,

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from

Write command can occur on any clock cycle following the previous Write command (refer to the following

figure).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

DQ's

NOP

WRITE A WRITE B

NOP

NOP

NOP

NOP

NOP

NOP

1 Clk Interval

DIN A0

DIN B0

DIN B1

DIN B2

DIN B3

Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)

TM Technology Inc. reserves the right

P. 9

to change products or specifications without notice.

Publication Date: FEB. 2007

Revision: A

Share Link: