T431616D Ver la hoja de datos (PDF) - Taiwan Memory Technology
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T431616D Datasheet PDF : 74 Pages
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tm TE
CH
T431616D/E
The Read command that interrupts a write burst without auto precharge function should be issued one cycle
after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data
must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to
the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not
be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DOUT B0 DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2 DOUT B3
DIN A0
don't care don't care
DOUT B0
DOUT B1
DOUT B2 DOUT B3
Input data for the write is masked.
Input data must be removedfrom the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals
tWR/tCK rounded up to the next whole number. In addition, the LDQM/UDQM signals must be used to mask input
data, starting with the clock edge following the last data-in element and ending with the clock edge on which the
BankPrecharge/PrechargeAll command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
WRITE
NOP
Precharge
NOP
tRP
NOP
Activate
NOP
ADDRESS
DQ
BANK
COL n
DIN
n
BANK (S)
tWR
DIN
n+1
ROW
: don't care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
TM Technology Inc. reserves the right
P. 10
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
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