T35L3232B Ver la hoja de datos (PDF) - Taiwan Memory Technology

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Fabricante

T35L3232B

SYNCHRONOUS BURST SRAM 32K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

FLOW-THROUGH READ TIMING

t KC

CLK

t KH t KL

t ADSS t ADSH

ADSP

t ADSS t ADSH

AD S C

t AS t AH

AD D RE S S

GW, BWE,

BW1-BW4

CE

(NOTE2)

A1

A2

t WS t WH

t CES t CEH

t AAS t AAH

AD V

OE

Q

t OEQ

t K Q LZ

tO EHZ

High-Z

t KQ

Q (A1 )

tO ELZ

t KQ

t KQX

Q (A2)

Q (A2 +1)

(NOTE 1)

Single R EAD

Preliminary T35L3232B

Des elec t Cy cle

(NO TE 4)

AD V s us pe nds burs t.

t KQHZ

Q (A2+2 )

Q (A2+3 ) Q(A2 )

Q (A2+1 ) Q (A2+2)

Burst wra ps aro und to

its inital state.

BURST READ

DON'T CARE

UNDEFINED

Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst

address following A2.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW

and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE

does not cause Q to be driven until after the following clock rising edge.

4. Output are disabled tKQHZ after diselect.

Taiwan Memory Technology, Inc. reserves the right P. 13

to change products or specifications without notice.

Publication Date: FEB. 2000

Revision:0.A

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