SY87700 Ver la hoja de datos (PDF) - Micrel

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Fabricante

SY87700

CDR EVALUATION KIT

Micrel 

Micrel

SY87700/701

Evaluation Board

FREQUENTLY ASKED QUESTIONS

What Do I Do with the Exposed Pad on the Bottom of

the Package?

The purpose of the exposed pad at the bottom of the

package is to conduct heat more efficiently out of the

package. Solder or use thermal conductive epoxy. Although

the pad is connected to VEE, will not be any degradation in

either output generated jitter or input jitter tolerance

performance.

I Just Got my Evaluation Board and I Cannot Get

Anything to Work.

First check the power supplies. This evaluation board

uses one power supply. You should see a current draw of

about 200mA when the part is running normally. After that,

check voltage swing levels of REFCLK. It is important to

focus on getting the synthesizer (CMU) to work first (REFCLK

to TCLK), before the data recovery side. TCLK synthesizer

sets up the coarse adjust for the VCO in the CDR (or CRU),

so if TCLK is not oscillating at the right frequency, the CDR

will not lock. Another tip: use a frequency counter like

HP53132A to measure frequency of TCLK– it is often more

foolproof than using the DSO. If using a DSO scope, like

the Agilent CSA803, or the 11801 from Tektronix, trigger off

of the REFCLK clock source.

After the synthesizer is operating as expected, make sure

to change the trigger on the oscilloscope to trigger on the

data generation instrument, such as second HP8133A, a

Microwave Logic 1400, or HP70004A,70841 BERT stack.

The BERT stack has a “clock output”, that be used to trigger

the scope. The instrument generating REFCLK is not phase/

frequency locked to the data generation side, so it would be

impossible to examine an “eye” diagram.

Check the eye of the output source directly first, before

going into the device. Most data generation instruments

have deskew capability. It is important to deskew both the

instrument and the ± coaxial cables into the DSO, otherwise

you’ll have too much apparent deterministic jitter.

Aside from setting the DIVSEL, and FREQSEL incorrectly,

everything should operate as expected at this point.

What is the Time Domain Reflectometry Test?

TDR (Time Domain Reflectometry) is used to verify

impedance continuity along a signal path. Many

interconnects, such as SMA, if not launched correctly onto

the PCB will exhibit inductive-like resonance with an abrupt

capacitive discontinuity. This discontinuity will subtract signal

from the inputs and outputs and effectively close the resulting

data eye.

What Should I Use to Generate REFCLK in My Design?

This depends on data rate, jitter budget, and cost.

However, REFCLK input jitter will affect the overall jitter

performance of the system. A fundamental tone crystal-

based oscillator is ideal. Measure the jitter of the oscillator

with a Wavecrest DTS2077. A measurement above the

3ps noise floor of the instrument is too high. Remember

that the REFCLK input is multiplied by the DIVSEL selected

value, so the resulting jitter increases by 20log (divide ratio).

If you use a clock derived from an ASIC, verify the single

cycle and accumulated cycle jitter.

Crystal based oscillators typically have poor AC power

supply rejection ratio, and if you are providing board power

via 400kHz switching supplies you may have to provide

some level of filtering, not just bypassing, for the supplies.

Also verify that the oscillator output has no “pedestals” in

the response due to improper impedance matching and/or

inadequate drive capability of the oscillator.

Do not use CMOS-based PLLs. They almost always have

too much high frequency deterministic jitter for this

application. Also fanning out one oscillator to several

locations on your board is not a good idea. Crosstalk and

inadequate drive can adversely affect performance. We

recommend Raltron, Mutron, CTS, Plantronics, Frequency

Management, etc., as vendors of crystal-based fundamental

tone oscillators.

Can you Suggest a Bypass/Decoupling Scheme?

The SY87700/701 data sheet contains the evaluation

board schematic, and a bill of materials list is included in

this document. We have found this arrangement to be an

excellent starting point. In addition, most system designs

could be dramatically improved by spacing the power planes

between ground planes to lower the self-inductance of the

power distribution.

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