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EM92547BN

CALLER ID FSK DECODER

ELAN Microelectronics 

EM92547A/B/D

CALLER ID FSK DECODER

With pin4 enabled, a portion of the power ring above 1.2V is fed to the ring counter

circuit. This circuit is a digital integrator. When the input signal at pin4 is above 1.2V,the

integrator is counting up at 800 Hz rate. Otherwise, counting down at 800Hz rate. A ring is

qualified when an internal count of binary 48 is reached and disqualified when an internal

count below binary 48.

Once the ring signal is qualified, the /RING INDICATOR will sent low. This can be

fed back to /PWR UP or can be used as an interrupt to an MCU. Once the /PWR UP pin is

below Vt-, the part will fully powered up, and ready to receive FSK. During this mode the

device current will increase to 3 mA typical.

* power up circuit

/PWR UP

RING /RD

DETECT

WAKE UP CLOCK

GEN

XTRL

The power up circuit accepts /PWR UP signal and /RD signal. In the power down

mode, if a ring signal is sent, the ring detector wakes up the oscillator and the main bias

generator. This in turn activates the IC. Once activated, a valid signal RD (ring detector) is

sent. Since no valid FSK single being detected, the whole IC will back to its power-down

mode after a period (default 3-second).

FSK data output(DATA OUT pin), FSK short data output(SHORTDATA) ,and FSK

carrier detect (/CD) :

As shown from functional block diagram, DATA OUT pin won’t have any FSK

decoding data until ‘Data Valid Energy Detect Circuit’ has detected enough energy and

timing (about 15ms) FSK signal coming. When this timing has been checked correctly,

open-drain carrier detect /CD pin will be pull low then DATA OUT pin will have decoding

data output. At this time, SHORTDATA pin will still not have any FSK decoding data until

enough energy and timing (about 12.5ms) FSK mark bits time have been checked. The

details timing about DATAOUT, SHORTDATA and /CD will be shown on Timing

Diagram for FSK timing.

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* This specification are subject to be changed without notice.

1998

~5~

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