SX1211I084TRT(2007) Ver la hoja de datos (PDF) - Semtech Corporation

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SX1211I084TRT
(Rev.:2007)

Lowest Power Integrated UHF Transceiver Short Range Devices

Semtech Corporation 

ADVANCED COMMUNICATIONS & SENSING

Index of Figures

Figure 1: SX1211 Block Diagram....................................... 5

Figure 2: SX1211 Pin Diagram .......................................... 6

Figure 3: Power Supply Breakdown................................. 12

Figure 4: Frequency Synthesizer Description .................. 13

Figure 5: LO Generator.................................................... 14

Figure 6: Loop Filter......................................................... 15

Figure 7: Transmitter Architecture.................................... 18

Figure 8: I(t), Q(t) Overview ............................................. 18

Figure 9: PA Control ........................................................ 20

Figure 10: Optimal Load Impedance Chart ...................... 21

Figure 11: Suggested PA Biasing and Output Matching .. 21

Figure 12: 869MHz Spectral Purity DC-1GHz.................. 22

Figure 13: 869MHz Spectral Purity 1-6GHz ..................... 22

Figure 14: Front-end Description ..................................... 23

Figure 15: Receiver Architecture...................................... 24

Figure 16: FSK Receiver Setting...................................... 24

Figure 17: OOK Receiver Setting..................................... 24

Figure 18: Active Channel Filter Description.................... 26

Figure 19: Butterworth Filter's Actual BW ........................ 27

Figure 20: Polyphase Filter's Actual BW .......................... 27

Figure 21: RSSI IRQ Timings........................................... 28

Figure 22: OOK Demodulator Description........................ 29

Figure 23: Floor Threshold Optimization.......................... 30

Figure 24: BitSync Description......................................... 31

Figure 25: SX1211’s Data Processing Conceptual View . 33

Figure 26: SPI Interface Overview and uC Connections.. 34

Figure 27: Write Register Sequence ................................ 35

Figure 28: Read Register Sequence................................ 36

Figure 29: Write Bytes Sequence (ex: 2 bytes)................ 36

Figure 30: Read Bytes Sequence (ex: 2 bytes)................ 37

SX1211

Figure 31: FIFO and Shift Register (SR)...........................37

Figure 32: FIFO Threshold IRQ Source Behavior.............38

Figure 33: Sync Word Recognition ...................................39

Figure 34: Continuous Mode Conceptual View.................40

Figure 35: Tx Processing in Continuous Mode .................40

Figure 36: Rx Processing in Continuous Mode.................41

Figure 37: uC Connections in Continuous Mode ..............41

Figure 38: Buffered Mode Conceptual View .....................43

Figure 39: Tx processing in Buffered Mode ......................44

Figure 40: Rx Processing in Buffered Mode .....................45

Figure 41: uC Connections in Buffered Mode...................46

Figure 42: Packet Mode Conceptual View........................47

Figure 43: Fixed Length Packet Format ...........................48

Figure 44: Variable Length Packet Format .......................49

Figure 45: CRC Implementation .......................................51

Figure 46: Manchester Encoding/Decoding......................52

Figure 47: Data Whitening ................................................52

Figure 48: uC Connections in Packet Mode .....................53

Figure 49: Optimized Rx Cycle .........................................56

Figure 50: Optimized Tx Cycle .........................................57

Figure 51: Tx Hop Cycle ...................................................58

Figure 52: Rx Hop Cycle...................................................59

Figure 53: Rx Tx Rx Cycle.......................................60

Figure 54: Reference Design’s Schematics......................69

Figure 55: Reference Design‘s Stackup ...........................70

Figure 56: Reference Design’s Layout (top view) .............70

Figure 57: 915 MHz SAW Filter Plot.................................71

Figure 58: 869 MHz SAW Filter Plot.................................71

Figure 59: Package Information........................................72

V3.0 – august 15th, 2007

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