STV7697B Ver la hoja de datos (PDF) - STMicroelectronics
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STV7697B Datasheet PDF : 18 Pages
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Circuit Description
STV7697B
All the data are kept memorized in the latch stage when the strobe input (STB) is pulled high.
The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input
(POL) at high level and forced to low level with POL at low level. The level of the power output is
inverted when the polarity command (POL) is pulled high.
Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the
POL input signal (Table 6).
Sustain current must not be sunk in the power output to VPP when the power supply is applied.
VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the
application.
Table 6: Power Output Truth Table
Pn*
CLR
STB
BLK
POL
Driver
Output
Comments
X
X
X
H
H
All H
Forced to High
X
X
X
H
L
All L
Forced to Low
H
L
L
L
L
H
Copy Data
L
L
L
L
L
L
Copy Data
H
L
L
L
H
L
Copy Inverted Data
L
L
L
L
H
H
Copy Inverted Data
X
X
H
L
L
Qn
Data Latched
X
X
H
L
H
Qn
Inverted Data Latched
X
H
L
L
L
L
All Low
X
H
L
L
H
H
All High
*Pn is the parallel output of the shift register (n = 1 to 64). Pn takes the value of serial input (SIN) after “n” shift
clock periods.
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