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STM1817TW7F

Low power reset circuit

STMicroelectronics 

STM1810/1811/1812/1813/1815/1816/1817/1818

2

Operation

Operation

2.1

Reset output

The STM181x asserts a reset signal to the Microcontroller (MCU) whenever VCC goes

below the reset threshold (VRST), and is guaranteed valid down to VCC = 1.0 V (0 °C to

105 °C). A microcontroller’s (MCU) reset input starts the MCU in a known state. The

STM1810 - STM1813/ STM1815 - STM1818 Low Power Reset circuits assert reset to

prevent code-execution errors during power-up, power-down, and brownout conditions

(Figure 8).

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for

the reset time-out period, trec. After this interval, RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period. Any time VCC goes below the reset threshold, the

internal timer clears. The reset timer starts when VCC returns above the reset threshold.

Reset trec is also triggered by an externally initiated rising edge on the RST pin

(STM1813/STM1818), following a low signal of 1.5 µs minimum duration.

2.2

Push-button detect reset (STM1813/1818)

Many systems require push-button reset capability (Figure 9), allowing the user or external

logic circuitry to initiate reset. On the STM1813/STM1818, a logic low on RST held for

greater than 1.5 µs asserts a reset. RST deasserts following a 100 ms minimum reset time-

out delay (trec). A manual reset input shorter than 1.5 µs may release RST without the

100 ms minimum reset time-out delay. To facilitate use with mechanical switches, the

STM1813/STM1818 contain internal debounce circuitry. A debounced waveform is shown in

Figure 10 The RST output has an internal 5.5 kΩ pull-up resistor.

2.3

Interfacing to bidirectional microcontrollers (MCU’s)

As the RST output on the STM1811/STM1816 is open drain, these devices interface easily

with MCU’s that have bidirectional reset pins. Connecting the µP supervisor’s reset (RST)

output directly to the microcontroller’s reset (RST) pin allows either device to assert reset

(Figure 11). No external pull-up resistor is required, as it is within the STM1811/STM1816.

2.4

Negative going VCC transients

The STM181x are relatively immune to negative-going VCC transients (glitches). Figure 20

shows typical transient duration versus reset comparator overdrive (for which the STM181x

will NOT generate a reset pulse). The graph was generated using a negative pulse applied

to VCC, starting at 0.5 V above the actual reset threshold and ending below it by the

magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width

a negative VCC transient can have without causing a reset pulse. As the magnitude of the

transient increases (further below the threshold), the maximum allowable pulse width

decreases. Any combination of duration and overdrive which lies under the curve will NOT

generate a reset signal. Typically, a VCC transient that goes 100 mV below the reset

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