STM-S3E Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Fabricante
STM-S3E Datasheet PDF : 16 Pages
| |||
Table 5
Pin Description
Pin #
1
2
3
4
5
6
7
internally.
8
internally.
9
10
11
12
13
freq.
14
15
16
17
18
Connection
Status 0
Status 1
LOR
PBO
GND
8 kHz Output
Reset
Tri-State
Hold Over Good
Mode Alarm
CNTL A
CNTL B
RFL
GND
Sync_Out
Future Use
GND
Clock_Out
19
Future Use
20
GND
21
External Reference 2
22
GND
23
External Reference 1
24
+5 VDC
Control Inputs
Table 6
Description
Mode indicator.
Mode indicator.
Loss of Reference indicator. 1 = active reference has been lost.
Phase build out indicator. 1 = module is in a phase build out condition.
Ground
Derived from Sync_Out.
Master reset for the module. A low pulse will reset the module. A logic low for a minimum of
1 µs is recommended to ensure a complete reset. This pin is pulled high
Tri-State control for all outputs. 1 = Hi-Z condition, 0 = Normal operation. Pin is pulled low
Indicates that the module has acquired enough data to provide an average Hold Over value.
Alarm indicator output. 1 = Alarm condition, 0 = Normal operation.
Mode control input. Pin is pulled low internally.
Mode control input. Pin is pulled low internally.
Reference frequency limit alarm for the phase locked loop. 1= Unit is ±15 ppm from Free Run
Ground
System clock output
Reserved for future use. Do not assert this pin
Ground
An independent, Stratum 3 clock output with the required ±4.6 ppm accuracy. May be used as
general purpose clock
Reserved for future use. Do not assert this pin
Ground
External reference #2 input
Ground
External reference #1 input
+5 Volt DC supply
Status Outputs
Table 7
CNTL B
0
0
1
1
CTNL A
0
1
0
1
Mode Selected
Free Run
Reference 1
Reference 2
Hold Over
Status 1
0
0
1
1
Status 0
0
1
0
1
Mode
Free Run
Reference 1
Reference 2
Hold Over
Preliminary Data Sheet #: TM012 Page 4 of 16 Rev: P06 Date: 05/20/ 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Share Link: 