STM1403CRMQ6F(2005) Ver la hoja de datos (PDF) - STMicroelectronics

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STM1403CRMQ6F
(Rev.:2005)

3V FIPS-140 Security Supervisor with Battery Switchover

STMicroelectronics 

STM1403

TAMPER DETECTION

Physical

There are four (4) high-impedance physical

tamper detect input pins, 2 normally set to High

(NH) and 2 normally set to Low (NL). Each input is

designed with a glitch immunity. These inputs can

be connected externally to several types of actua-

tor devices (e.g., switches, wire mesh). A tamper

on any one of the four inputs that causes its state

to change will trigger the security alarm (SAL) and

drive it to active-low. Once the tamper condition no

longer exists, the SAL will return to its normal High

state.

TP1 and TP3 are set Normally to High (NH). They

are connected externally through a closed switch

or a high-impedance resistor to VOUT (in the case

of STM1403A) or VTPU (in the case of STM1403B/

C), A tamper condition will be detected when the

input pin is pulled low. If not used, tie the pin to

VOUT or VTPU.

TP2 and TP4 are set Normally to Low (NL). They

are connected externally through a high-imped-

ance resistor or a closed switch to VSS. A tamper

condition will be detected when the input pin is

pulled high. If not used, tie the pin to VSS.

Supply Voltage

The internally switched supply voltage, VINT (ei-

ther VCC input or VBAT input) is continuously mon-

itored. If VINT should exceed the over voltage trip

point, VHV (set at 4.2V, typical), or should go below

the under voltage trip point, VLV (set at 2.0v, typi-

cal). SAL will be driven active-low. Once the

tamper condition no longer exists, the SAL pin will

return to its normal High state.

When no tamper condition exists, SAL is normally

High.

When a tamper is detected, the SAL is activated

(driven low), independent of the part type. VOUT

can be driven to one of three states, depending on

which variant of STM1403 is being used (see De-

vice Options, page 1):

■ ON;

■ High-Z; or

■ Ground (VSS).

Note: The STM1403 must be initially powered

above VRST to enable the tamper detection

alarms. For example, if the battery is on while VCC

= 0V, no alarm condition can be detected until VCC

rises above VRST (and trec expires). From this

point on, alarms can be detected either on battery

or VCC. This is done to avoid false alarms when

the device goes from no power to its operational

state.

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