STLVDS385 Ver la hoja de datos (PDF) - STMicroelectronics
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STLVDS385
STMicroelectronics
STLVDS385 Datasheet PDF : 14 Pages
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STLVDS385
TRANSMITTER SWITCHING CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise
noted. Typical values are referred to TA = 25°C)
Symbol
Parameter
Test
Conditions
Min.
Typ.
Max.
Unit
tLLHT
tLLLT
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tSTC
tHTC
tCCD
LVDS Low-to-High Transition Time (Fig. 4)
LVDS High-to-Low Transition Time (Fig. 4)
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
TxIN Setup to TxCLK IN (Fig. 6)
TxIN Hold to TxCLK IN (Fig. 6)
TxCLK IN to TxCLK OUT Delay (Fig. 7)
tCCD
tJCC
TxCLK IN to TxCLK OUT Delay (Fig. 7)
Transmitter Jitter Cycle-to-Cycle (Fig. 12 - Note 4)
tPLLS
tPDD
Transmitter Phase Lock Loop Set (Fig. 8)
Transmitter Power Down Delay (Fig. 10)
0.75 1.5
ns
0.75 1.5
ns
f = 40 MHz -0.25
0
0.25 ns
3.32 3.57 3.82 ns
6.89 7.14 7.39 ns
10.46 10.71 10.96 ns
14.04 14.29 14.54 ns
17.61 17.86 18.11 ns
21.18 21.43 21.68 ns
f = 65 MHz -0.20
0
0.20 ns
2.00 2.20 2.40 ns
4.20 4.40 4.60 ns
6.39 6.59 6.79 ns
8.59 8.79 8.99 ns
10.79 10.99 11.19 ns
12.99 13.19 13.99 ns
f = 85 MHz -0.20
0
0.20 ns
1.48 1.68 1.88 ns
3.16 3.36 3.56 ns
4.84 5.04 5.24 ns
6.52 6.72 6.92 ns
8.20 8.40 8.60 ns
9.88 10.08 10.28 ns
2.5
ns
0
ns
TA = 25°C,
3.8
VCC = 3.3V
2.8
6.3
ns
7.1
ns
f = 85 MHz
f = 65 MHz
110 150
ps
210 230
f = 40 MHz
350 370
10
ms
100
ns
Note 1: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ∆VOD).
Note 2: VOS previously referred as VCM.
Note 3: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and tempera-
ture range. This parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter
is measured with a cycle-to-cycle jitter of ± 3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A
jitter event of 3ns, represents worse case jump in the clock edge from most graphics controller VGA chips currently available.
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal
switching needed to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
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