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STLVDS385 Ver la hoja de datos (PDF) - STMicroelectronics

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STLVDS385 Datasheet PDF : 14 Pages
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STLVDS385
PIN CONFIGURATION
PIN DESCRIPTION
PlN N°
1, 9, 26
2, 3, 4, 6, 7, 8, 10, 11, 12,
14, 15, 16, 18, 19, 20, 22,
23, 24, 25, 27, 28, 30, 50,
51, 52, 54, 55, 56
5, 13, 21, 29
17
31
32
33, 35
34
36, 43, 49
37, 41, 45, 47
38, 42, 46, 48
39
40
44
SYMBOL
VCC
TXIN
NAME AND FUNCTION
Power Supply pins for TTL Inputs
TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control lines-
FPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC,
Data Enable)
GND
R_FB
TxCLKIN
PWRDWN
PLL GND
PLL VCC
LVDS GND
TxOUT+
TxOUT-
TxCLK OUT+
TxCLK OUT-
LVDS VCC
Ground pins for TTL Inputs
Programmable strobe select (See Table 1)
TTL level clock input. Pin name TxCLK IN
TTL level input. When asserted (low input) TRI-STATES the outputs,
ensuring low current at power down
Ground pins for PLL
Power Supply pin for PLL
Ground pins for LVDS outputs
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential clock output
Negative LVDS differential clock output
Power Supply pin for LVDS outputs
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