DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

STLC2500 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza
componentes Descripción
Fabricante
STLC2500
ST-Microelectronics
STMicroelectronics ST-Microelectronics
STLC2500 Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
STLC2500
Table 14. STLC2500 pin list (Test)
Name
Analogue test pin
VDD_T
ABUS_IN_QN
ABUS_QP_IP
ABUS_IP_QP
ABUS_QN_IN
ANA_1
PIN #
C06
A08
A09
B07
B08
A10
ANA_2
B04
ANA_3
C10
ANA_4
D09
AF_PRG
K10
(1) To be strapped to VSS_ANA
Description
Test supply
Test pin
Test pin
Test pin
Test pin
Analogue test pin
(Leave unconnected)
Analogue test pin
(Leave unconnected)
Analogue test pin
(Leave unconnected)
Analogue test pin
(Leave unconnected)
Test pin (Leave unconnected)
DIR
Reset Default
VDDIO
I/O
Input (1) Input (1)
I/O
Input (1) Input (1)
I/O
Input (1) Input (1)
I/O
Input (1) Input (1)
I/O
Open
Open
Table 15. STLC2500 pin list (Configuration)
The configuration pins are used to select different modes of operation for the chip:
Digital or analogue incoming system clock
CONFIG_CLK =’1’
CONFIG_CLK =’0’
Initiated Low Power modes
CONFIG_JS =’0’ AND CONFIG_M = ‘0’
CONFIG_JS =’0’ AND CONFIG_M = ‘1’
CONFIG_JS =’1’ AND CONFIG_M = ‘0’
CONFIG_JS =’1’ AND CONFIG_M = ‘1’
The incoming system clock is a digital square signal.
(See chapter 3.4.)
The incoming system clock is a sine wave signal.
(See chapter 3.4.)
Reserved
Initiated low power, mode 1. (See chapter 7.8.)
Initiated low power, mode 2. (See chapter 7.8.)
Reserved
Where '1' means VDD_IO_A and '0' means VSS_DIG.
The other two configuration pins, CONFIG_RF and CONFIG_R have to be strapped to VSS_DIG.
6 FUNCTIONAL DESCRIPTION
6.1 Transmitter
The transmitter uses the serial transmit data from the baseband. The transmitter modulator converts this
data into GFSK modulated I and Q digital signals. These signals are then converted to analogue signals
that are low pass filtered before up-conversion. The carrier frequency drift is limited by a closed loop PLL.
6.2 Receiver
The STLC2500 implements a low-IF receiver for Bluetooth modulated input signals. The radio signal is
taken from a balanced RF input and amplified by an LNA. The mixers are driven by two quadrature LO
signals, which are locally generated from a VCO signal running at twice the frequency. The I and Q mixer
output signals are band pass filtered by a poly-phase filter for channel filtering and image rejection. The
8/23

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]