STK15C68 Ver la hoja de datos (PDF) - Simtek Corporation
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STK15C68 Datasheet PDF : 10 Pages
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STK15C68
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
AutoStore™ OPERATION
The STK15C68 uses the intrinsic system capaci-
tance to perform an automatic store on power
down. As long as the system power supply takes at
least tSTORE to decay from VSWITCH down to 3.6V, the
STK15C68 will safely and automatically store the
SRAM data in Nonvolatile Elements on power
down.
In order to prevent unneeded STORE operations,
automatic STORE will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK15C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK15C68 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs
during low-voltage conditions. When VCC < VSWITCH,
software STORE operations and SRAM WRITEs are
inhibited.
LOW AVERAGE ACTIVE POWER
The STK15C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC= 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK15C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
100
100
80
80
60
40
TTL
20
CMOS
0
50
100 150 200
Cycle Time (ns)
Figure 2: ICC (max) Reads
60
TTL
40
CMOS
20
0
50
100 150 200
Cycle Time (ns)
Figure 3: ICC (max) Writes
March 2006
8 Document Control # ML0009 rev 0.2
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