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STA003T

MPEG 2.5 LAYER III AUDIO DECODER

STMicroelectronics 

STA003T

Figure 4. MPEG Decoder Interfaces.

MASTER CLK

SRC-INT

SDI

CHANNEL

DECODER

SCKR

BIT_EN

µP

XTO FILT

IIC

XTI

SCL

SDA

PLL

IIC

MPEG

DECODER

SERIAL AUDIO INTERFACE

RX

TX

SDO

SCKT

LRCKT

DAC

D97AU665A

Figure 5. Serial Input Interface Clocks

SDI

OCLK

DATA IGNORED

SCKR

SCLK_POL=0

SCKR

SCLK_POL=2

BIT_EN

D98AU968

2.2 - Serial Input Interface

STA003T receives the input data thought the Se-

rial Input Interface (Fig.4). It is a serial communi-

cation interface connected to the SDI (Serial Data

Input) and SCKR (Receiver Serial Clock).

The interface can be configured to receive data

sampled on both rising and falling edge of the

SCKR clock.The BIT_EN pin, when set to low,

forces the bitstream input interface to ignore the

incoming data. The possible configurations are

described in Fig. 5.

The bitstream must be sent MSB first to

STA003T.

2.3 - PLL & Clocks Generation System

The STA003T has a clock generation system that

is used by the device core to adjust the core

speed, for power saving, adapting the processing

speed to the needs of the decoded audio pro-

gram. The clocks generation system is even used

to generate all the PCM output interface clocks:

SCKT, LRCKT, and OCLK.

The block diagram in Fig. 6 is a description of

STA003T clocks generation system. The input of

STA003T clocks system is a 14.72MHz input

clock.

Internally it is composed by a PLL loop, and the

VCO output is fed into a divider stage, used to

program the Core speed and the PCM interface

clocks. Several registers are programmed by the

Layer III decoder core, and by the user, when a

specific interface configuration is required.

The PLL can be programmed by a set of regis-

ters, as described in the I2C Registers section,

The particularity of the STA003T clocks genera-

tion system is the possibility to modify the Audio

Sampling Frequency (LRCKT) in steps of few

ppm to compensate dynamically the audio sam-

pling rate offset between the receiver and the

broadcasting station.

The compensation is done by the STA003T core

without requiring interaction with the application

controller and the sampling rate compensation

produces a jittering effect outside the audible

range.

The device implements a sampling rate offset

control receiving by STA002 (WorldSpace Chan-

nel Decoder) a dedicated signal every decoded

Broadcast Channel Frame (432ms).

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