ST95022 Ver la hoja de datos (PDF) - STMicroelectronics
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ST95022 Datasheet PDF : 16 Pages
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Figure 11. WRSR: Write Status Register Sequence
ST95022
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
INSTRUCTION
STATUS REG.
D
HIGH IMPEDANCE
Q
AI01445
Page Write Operation
A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting the device after the first
byte of data, up to 15 additional bytes can be shifted
in prior to deselecting the chip. A page address
begins with address xxxx 0000 and ends with xxxx
1111. If the address counter reaches xxxx 1111 and
the clock continues, the counter will roll over to the
first address of the page (xxxx 0000) and overwrite
any previously written data. The programming cy-
cle will only start if the S transition occurs just after
the eighth bit of data of a word is received.
POWER ON STATE
After a Power up the ST95022 is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unchanged (non-volatile
bits).
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Ta-
ble 5.
– Non valid S and HOLD transitions are not
taken into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the cycle status register),
that is the Chip Select S must rise during the
clock pulse following the introduction of a multi-
ple of 8 bits.
– Access to the memory array during non-vola-
tile programming cycle is ignored; however,
the programming cycle continues.
– After any of the operations WREN, WRDI,
RDSR is completed, the chip enters a wait
state and waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is
brought low.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.
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