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ST7038-0B Ver la hoja de datos (PDF) - Sitronix Technology Co., Ltd.

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ST7038-0B
SITRONIX
Sitronix Technology Co., Ltd. SITRONIX
ST7038-0B Datasheet PDF : 63 Pages
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ST7038
Figure 1 The 4-Line SPI Mode access timing
Figure 2 The 3-Line SPI Mode access timing
I2C Interface (PS[2:0] = "1, 0, 0")
The I2C Interface uses two-signal to communicate between different ICs or modules. The two signals are SDA (Serial Data)
and SCL (Serial Clock). Both lines must be connected to a pull-up resistor to provide the “H” voltage level. Data transfer may
be initiated only when the bus is not busy.
ST7038i support I2C interface with only write function. Status read or data read is impossible (except reading the
Acknowledge signal). The related signals are listed below:
SCL: serial clock input
SDA_IN: serial data input
SDA_OUT: acknowledge response output
SA1~SA0: select the slave address and the available slave addresses are: “0111100” to “0111111”.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer
is illustrated in Figure 3.
START AND STOP CONDITIONS
Both SDA and SCL lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on SDA while SCL is HIGH
is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 4.
SYSTEM CONFIGURATION
The system configuration of I2C interface is illustrated in Figure 5. The related glossaries are listed below:
Transmitter: the device sends the data to the bus
Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the
message
Arbitration: a procedure to ensure that, if more than one master tries to control the bus simultaneously, only one
is allowed to do so and the message is not corrupted
Synchronization: a procedure to synchronize the clock signals of two or more devices.
Ver 1.3
15/63
2008/05/27

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