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ST5451

ISDN HDLC AND GCI CONTROLLER

STMicroelectronics 

ST5451

EOM2

XAB2

RMR2

RAB2

XMR2

End of Message 2 (monitor channel)

MON2 has received an end of mes-

sage.

Monitor Transmit ABORT

The received byte has not been de-

tected in two successive frames.

MON2 has sent an ABORT (A bit) to

the remote transmitter.

Receive Monitor Register 2 ready

A byte has been received in register

MONR2.

Receive ABORT

MON2 received an ABORT from the re-

mote receiver.

Transmit Monitor Register 2 ready

A byte can be stored in register

MONX2.

MASK0, MASK1, MASK2

After Reset FF; the three mask registers MASK0,

MASK1, MASK2 are associated respectively to

the three interrupt registers ISTA0, ISTA1,and

ISTA2.

Each interrupt source in ISTA registers can be se-

lectively masked by setting to ”1” the correspond-

ing bit in MASK1. Interrupt sources (masked or

not) are indicated when ISTA is read by the mi-

croprocessor. When an interrupt source is not

masked, INT goes low.

STAR Status Register

After Reset 48H

XDOV XFW IDLE RLA DCIO 0 0 0

XDOV

XFW

IDLE

RLA

DCIO

Transmit Data Overflow

More than 32 bytes have been written

into the XFIFO.

XFIFO Write enable

Data can be entered into the XFIFO.

IDLE State

15 or more consecutive ones have

been detected on the input data line.

Receive Line Active

Frames or interframe flags are being

received

D and C/I Channels are occupied

8/34

CMDR Command Register

After Reset 00

XHF XME RMC RMD RHR XRES M2RES M1RES

XHF

XME

RMC

RMD

RHR

HDLC frame transmission can start.

Transmit Message End

The last part of the frame was entered

in XFIFO and can be sent.

Receive Message Complete

Reaction to RPF or RME interrupt. The

received frame (or one pool of data)

has been read and the corresponding

RFIFO is free.

Receive Message Delete

Reaction to RPF or RME interrupt. The

entire frame will be ignored. The part of

frame already stored is deleted.

Reset HDLC receiver

XRES

Reset HDLC transmitter

XFIFO is cleared and the transmitted

frame (if any) is aborted.

M2RES Monitor 2 Reset

Reset MONITOR and C/I channels (TX

and RX).

M1RES Monitor 1 Reset

Reset MONITOR and C/I channels (TX

and RX).

*

For the four first bits (XHF, XME, RMC,

RMD), the reset is done by the device;

the other bits level sensitive

MODE HDLC Mode Register

After Reset 00

DMA FL1 FL0 ITF RAC CAC NHF FLA

DMA DMA Interface activation

FL1/0

Frame Length

Minimum frame length accepted

FL1

FL0

3 bytes

0

0

4 bytes

0

1

5 bytes

1

0

6 bytes

1

1

ITF

RAC

InterframeTime Fill

ITF= 1 : Flags are transmitted

ITF= 0 : IDLE is transmitted

RAC= 1 : Activate RX

RAC= 0 : deactivate RX

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